EMRFD Message Archive 6895
Message Date From Subject 6895 2011-11-26 07:03:26 jasonb1963 Best Practices for PCBs Hi,
I am thinking of having some PC boards made for the portable SDR I mentioned earlier on this list.
Would like to put the entire system on a single PCB rather than breaking it up into several PCBs in order to simplify construction and keep the costs down. I lack the ability to fabricate the nice metal shielding which I see on many commercial PCBs with receivers in them.
I would like to make up for the above disadvantages by employing other techniques to minimize interference from some subsystems (e.g. digital or TX) to sensitive subsystems (RX front end).
Below is a list of practices I am intending to follow:
1) Maximize physical separation between digital, switching regulator, and TX circuits from the front end circuits of the RX.
2) Bypass all digital chips with a bypass capacitor physically close to the chip.
3) Pour separate ground planes for each subsystem on the PC board and then connect them together with a regular trace.
4) Use RC filters on the positive power rails of each subsystem on the PC board, possibly excepting the RF PA which can be directly connected to the battery.
5) Follow Wes' advice in EMRFD by using several identically valued capacitors to bypass power rails rather than the usual mix of low and high-valued capacitors.
Do all of these make sense and are there any other practices I should be considering?
6896 2011-11-26 07:39:41 Shawn Upton Re: Best Practices for PCBs My only thought is that the ground plane connections can represent as much of an impedance as anything else. On the few designs I've done (not RF) I have instead notched the GND plane, mostly to keep cross currents (say from power supplies) from going under a sensitive IC (say an ADC). But, when I do that, I have to pay particular attention to how the i/o lines leave that island. Those i/o traces need GND under; it is not wise for the high speed digital lines to "jump over" my GND plane notch.
How are you bringing signals from one end of the PCB to the other? Coax runs, or PCB trace? If coax, then I see less issues with your idea of separate GND islands. OTOH if it's traces then I think a more continous GND plane is on order.
Finally, have you looked at board houses yet? I know it's not in vogue to use muli-layer boards for hobby projects; but for a small bump in price you might find 4 layer isn't that much of a bump. You could then use that stackup to your advantage. I'm thinking two internal GND planes, possibly not the same "GND", and installation of SMT parts on both sides. I don't know what frequencies you are using, but I don't think your 1oz copper GND plane will get much isolation between the two sides of the plane, hence, using two planes. Would just need to make sure via's going to GND only hit one GND plane, except one in the corner to make the two at the same DC potential. You could do digital on one side, analog on the other; however, passing signals between the two sides might be more tricky than I'm thinking (need to observe good ground return path practices).
Shawn Upton, KB1CKT
6897 2011-11-26 09:03:50 John Levreault Re: Best Practices for PCBs I've found this very helpful:
de John NB1I
6907 2011-11-26 19:03:23 jasonb1963 Re: Best Practices for PCBs Hi John,
Thanks for the reference.
It is interesting to note that the reference suggests paralleling multiple capacitors of different values for power supply bypassing -- "Paralleling different capacitor values helps ensure that the power supply pins see a low ac impedance across a wide band of frequencies." This directly conflicts advice Wes gives in EMRFD:
"Traditional lore tells us that the bandwidth for bypassing can be extended by paralleling a capacitor what works well at once frequency with another to accommodate a different part of the spectrum. [...] The results are terrible!" (p2.29)
Can anyone shed any light
6908 2011-11-26 19:11:04 jasonb1963 Re: Best Practices for PCBs Hi Shawn,
Thanks for your reply. The analog parts of the board all run at under 30MHz, but the digital side will run up to 120MHz with harmonics obviously going quite a bit higher still.
I've looked into having 4-layer boards made. Frankly, having double-sided boards made is very cheap, but as soon as you go to 4-layer boards, the prices jumps by a factor of 10 or so. There are some places in China that undercut all of the board houses in the West by a large amount, but I haven't found any that do more than 2-layer boards yet.
I'm still working
6909 2011-11-26 19:47:33 Dave Re: Best Practices for PCBs I have boards done by pcbcart.com in China. Their 4 layer boards are
about twice the price of a 2 layer board.
Dave - WB6DHW
6910 2011-11-26 20:38:19 Ashhar Farhan Re: Best Practices for PCBs jason,
there are several advantages to keeping things on separate boards. the
biggest of them is that each module can be shielded.
in fact, purely from constructional point of view, i'd say a module is
that which has the least number of connections running in and out of
many a times, we insist on so aggressively shielding our rf line-up
that we use rf tight enclosures with radial bypass capacitors,etc. and
they do make a difference.
shielding alone will not make it all well, the interconnects between
various modules has to be through transmission lines. this is not an
overkill but a simple way of transferring rf energy (not 'voltage')
across various parts of the rig.
these are tried and tested methods. even in designs as primitive as
bitx, i have seen the dramatic drop in dynamic range, noise and
breakthroughs between the kits build over a single pcb vs ugly,
so, if we are limiting ourselves to a single board, each module should
be on a separate ground island, the interconnects should be through
co-ax runs and there should be soldered shields around each module.
those appear to be the basic rules of thumb.
6911 2011-11-26 21:56:12 John Kolb Re: Best Practices for PCBs As I understand it, any capacitor has a self resonant freq, where the
capacitive reactance is equal
to the inductive reactance of the connecting leads. Above this freq,
the C looks like an L. If you now
put a smaller C in parallel with this component which is effectively
an L, you've created an LC circuit
which will be resonant at some freq - at that freq, it's very high
impedance, and thus not a bypass.
I still see data sheets with large and small C's in parallel however.
With a 4 layer PCB, you are putting a large C, the bypass cap, in
parallel with a small C, the C between
the power and gnd planes of the PCB. Nobody says this is a bad
thing. I'm also told that when the IC
draws current to supply an output changing, the initial current surge
comes from the Vcc/gnd PCB cap.
The current from the bypass cap is slower because of lead inductance.
At 07:03 PM 11/26/2011, you wrote:
>Thanks for the reference.
>It is interesting to note that the reference suggests paralleling
>multiple capacitors of different values for power supply bypassing
>-- "Paralleling different capacitor values helps ensure that the
>power supply pins see a low ac impedance across a wide band of
>frequencies." This directly conflicts advice Wes gives in EMRFD:
>"Traditional lore tells us that the bandwidth for bypassing can be
>extended by paralleling a capacitor what works well at once
>frequency with another to accommodate a different part of the
>spectrum. [...] The results are terrible!" (p2.29)
>Can anyone shed any light
6912 2011-11-27 01:15:43 Leon Heller Re: Best Practices for PCBs On 27/11/2011 03:03, jasonb1963 wrote:
> Hi John,Using as as many as three different values in parallel for decoupling is
> Thanks for the reference.
> It is interesting to note that the reference suggests paralleling
> multiple capacitors of different values for power supply bypassing --
> "Paralleling different capacitor values helps ensure that the power
> supply pins see a low ac impedance across a wide band of frequencies."
> This directly conflicts advice Wes gives in EMRFD:
> "Traditional lore tells us that the bandwidth for bypassing can be
> extended by paralleling a capacitor what works well at once frequency
> with another to accommodate a different part of the spectrum. [...] The
> results are terrible!" (p2.29)
> Can anyone shed any light on this? I'm inclined to trust what Wes has
> written in EMRFD and ignore this part of the guide.
recomemmended for very high-performance devices, such as FPGAs. They can
have a hundred or more supply connections, which means *lots* of capacitors.
6914 2011-11-27 05:55:47 Shawn Upton Re: Best Practices for PCBs I don't have EMFD in front of me; but I believe the warning was against using say 0.1uF mono for "high frequency", and a 100uF electrolytic for "low frequency". The SRF's are so far apart that there are huge areas of non-bypass.
Most recommendations I've seen lately seem to do no more than a decade jump. 1nF, 10nF and 100nF, then 1uF (maybe a bit larger) tantalum and finally the buss capacitor on the supply. Lots of capacitors, and of course the larger values can be located further away from the point needing bypassing. The reason for decade value jumps is that the SRF moves around by something like the value of 3 (for similar construction capacitors); having three or more values in parallel means that one capacitor goes inductive another one starts becoming dominate.
Shawn Upton, KB1CKT
6915 2011-11-27 06:00:58 Shawn Upton Re: Best Practices for PCBs 10 years ago I used to use Sierra Proto Express's No Touch for simple boards. I want to say $115 for 2 layer boards, and $153 for 4 layer? Three boards would be given at that price, 5 day turn. Looks like you have to register now, though, in order to get a quote. They are likely more expensive too now.
4pcb.com should still have good pricing. They have free quotation, and a free DFM check too.
Shawn Upton, KB1CKT
6916 2011-11-27 06:44:38 jasonb1963 Re: Best Practices for PCBs Hi Dave,
The url "pcbart.com" and "www.pcbart.com" do not resolve for me. There is a "pcb-art.com" but it's a company in Canada. I would love to find a cheap PCB manufacturer in China that does 4-layer boards, so if you have another URL for them, I'd like to know about it.
Here is the cheap 2-layer service in China I was planning to use for my 2-layer boards: http://www.seeedstudio.com/depot/fusion-pcb-service-p-835.html?cPath=185
By the way, I like the work you have done on your UHFSDR and am using some of your ideas in my own work.
6917 2011-11-27 06:52:10 jasonb1963 Re: Best Practices for PCBs Hi Farhan,
I'm sure you're right about using separate boards. But since I'm doing this on a hobbyist budget and trying to keep the end result relatively small (portable), I have to make certain compromises. I'm trying to understand the nature of the compromises I'm making so that I can make them intelligently rather than haphazardly.
If I can have 4-layer boards made, I think it may go a long way to making up for using separate boards.
Building RF tight enclosures to put
6918 2011-11-27 07:05:26 jasonb1963 Re: Best Practices for PCBs Hi Shawn,
In EMRFD, Wes gives an example of paralleling a 470pF capacitor with a 0.01uF capacitor and shows that a high frequency response is created at 63MHz based on his assumption that each capacitor had a series inductance of 7nH. Obviously if you are using SMT components (and I am), this inductance will be lower, but that only pushes the resonance up to higher frequencies.
He goes on to say, "Bypassing can be improved by paralleling. However, the capacitors should be approximately identical. Fig 2.91 shows the result of paralleling two capacitors of about the same value. They differ slightly at 390 and 560pF, creating a hint of resonance. This appears as a small 'burble' in the reactance plot and a tiny loop on the Smith Chart..."
Wes suggests that tantalum electrolytic capacitors are effective when you need to bypass lower frequencies and still want to bypass RF as well (audio/IF stages).
I too find it curious that in most professional literature I have read, the practice of using different capacitor values in parallel is used. However, until I find circuits designed by someone like Jim Williams suggesting the use of this technique, I think I'll continue to take Wes' advice and avoid it.
6920 2011-11-27 09:14:49 Lasse Re: Best Practices for PCBs Guess you missed a letter...
Only heard good from them... not used it myself though.
jasonb1963 skrev 2011-11-27 15:44:
> Hi Dave,
> The url "pcbart.com" and "www.pcbart.com" do not resolve for me. There is a "pcb-art.com" but it's a company in Canada. I would love to find a cheap PCB manufacturer in China that does 4-layer boards, so if you have another URL for them, I'd like to know about it.
> Here is the cheap 2-layer service in China I was planning to use for my 2-layer boards: http://www.seeedstudio.com/depot/fusion-pcb-service-p-835.html?cPath=185
> By the way, I like the work you have done on your UHFSDR and am using some of your ideas in my own work.
6921 2011-11-27 09:14:49 John Levreault Re: Best Practices for PCBs I've had very good results with PCBWing (www.pcbwing.com). They have an on-line
calculator that gives pricing and allows you to adjust quantity and delivery
time. Their quality and customer service are top-notch.
6933 2011-11-29 10:41:10 groundplane1 Re: Best Practices for PCBs Hi,
Reading this thread reminded me of a calculator tool that may be helpful.
(free download using excel).
It's quite informative to play arround with capacitor values and see the efect of paraleling, and the problematic parallel resonances that can occer with different values.
It looks as though if you use differet values, then many (3 per decade or more) values and a 'lossy' electrolytic are helpful in controling the paralel rosonances.
The end game is always to achieve a low enough impedance across the frequency range involved.
6934 2011-11-29 11:08:48 William Carver Re: Best Practices for PCBs On Tue, 2011-11-29 at 18:40 +0000, groundplane1 wrote:
>N2PK, designer of his own VNA, told me that once at IBM he used an hp
> Reading this thread reminded me of a calculator tool that may be
> (free download using excel).
> It's quite informative to play arround with capacitor values and see
> the efect of paraleling, and the problematic parallel resonances that
> can occer with different values.
> It looks as though if you use differet values, then many (3 per decade
> or more) values and a 'lossy' electrolytic are helpful in controling
> the paralel rosonances.
> The end game is always to achieve a low enough impedance across the
> frequency range involved.
> 73 Trevor
VNA on a big logic board, choosing position/size of bypasses and
groundplane layout to obtain minimum supply impedance over the whole
board. Its not a trivial matter.
Every bypass has some internal inductance, so at some frequency its
series resonant and a really GREAT bypass there. Above that it becomes
inductive, instead of capacitive. That inductance is small, like a very
short piece of wire, so by itself it's not necessarily deadly. But it
can be resonant with other bypasses that have not reached their series
resonant frequency. For example, a .01 uF might be series resonant at 20
MHz while the parallel .001 uF is resonant at 120 MHz. Somewhere above
20 MHz there is a parallel resonance between the inductance of the .01
and the remaining capacitance of the .001 uF.
This parallel resonance is damped by the ESR of both capacitors, as well
as physical layout and other things (say ferrite beads) connected to
that node. So it might not produce a high Q resonance that causes a
But it depends upon so many aspects of board layout and capacitor ESR
that be aware it MIGHT jump up and bite you. For example in that
hypothetical .01 and .001 case I described, you might be driven nuts
with an amplifier that is unstable on 10m, even though it works
perfectly on 15m. In that hypothetical amplifier you might, for example,
replace the .01 uF with two .005 uF in parallel, who don't become series
resonant until 35 MHz, and find the amplifier becomes stable on 10m even
though the total bypass capacitance hasn't changed.
Strange problems do sometimes arise so it's something to be aware of.
Experienced designers like Wes have a BIG bag of tricks.
6936 2011-11-30 10:04:37 boblarkin02 Re: Best Practices for PCBs 6937 2011-12-02 11:38:56 Dean Blake Re: Best Practices for PCBs Question... is it a good idea then in circuits, with say an LM386
audio stage that is used in a homebuilt transceiver (where RF might exist on the Bus) to bypass the bus lines with say multiple caps..
47ufd paralleled with say a .1ufd so that there is minimal series
L to the RF currents (as opposed to a single larger electrolytic)
and do this in linear fashion
6938 2011-12-02 16:47:26 boblarkin02 Re: Best Practices for PCBs Hi Dean - I suspect that the single electrolytic on the power pin of the 386 would be quite adequate. Probably unneeded, but available as a precauti 6940 2011-12-03 08:15:06 w8nf Re: Best Practices for PCBs I'm glad someone else brought up ESR. That's ultimately what saves the design. If the capacitors were zero-loss, then parallleling two caps of different values would generate a complete absence of bypassing at a frequency inbetween the series resonsnant points of the two capacitors. However, due to finite Q of both caps, the in-between resonance is damped. The closer together the two capacitors SRFs, the more damping is caused by a finite ESR.
This is not merely an exercise in thinking. You ALWAYS have at least two caps in parallel. With just one bypass cap at the chip, it is already in parallel with the output capacitor of your power supply.
I have had to come up with bypass arrangements inside IC packages, where the device drew 3,000 amp peak current due to simultaneous switching. We used lots of small bypass caps inside the IC package (as many as 200), then a somewhat larger size outside on the PCB, directly under the BGA, then one more layer. But the third layer of larger caps was isolated from the second layer by ferrite beads, which very much tamed the "bad" resonance that was in between two "good" resonances.
A VNA is a great tool, but if you have an RF signal generator and any of the various power meter designs, you have the right tools. Feed the RF sig gen into the intended DC power trace for the PCB, and place the power meter on a proposed location for an IC. You'll find out if you have any problem frequencies.
Those who are fluent in LTSpice may choose to test this out. Make a circuit with two parallel caps, with a 10:1 ratio of C. Put some fixed inductance in series with each, say 10nH. Add a swept freq source with series resistance, and a load. 50 ohms for each isn't a bad start. Now look at the frequency response. You will indeed, see a frequency where the two bypass caps are doing nothing at all. Now, place resistance in sereies with each cap - not much, like 0.1 ohm (that happens to be the ESR that I have measured on many larger chip caps). Notice how much that peak declines.
Also, when designing your bypass circuits, understand that they have essentially three functions, and you may design differently depending on their function. One function is to ensure that there's adequate pulse current available to the IC in question...very important for CMOS logic ICs. Another is to prevent IC (or circuit) generated noise from getting "out" onto the DC line, and the third is to keep DC power supply noise away from the circuit being bypassed.
For most simple ham designs, tossing a bypass cap across each circuit works, but if you're after high dynamic range, you probably need to start considering the DC feed and bypass system as an entire circuit
6941 2011-12-03 10:27:05 William Carver Re: Best Practices for PCBs Bypassing, like other aspects of design, is like the layers of an onion.
Sometimes understanding the top layer (Xc=1/2*pi*f*C) is sufficient,
other times you have to peel more layers off, understanding in more
Simply knowing that there are subtle issues in bypassing is a first
step. Then, even if you have degrees, building things, measuring things
like ESR, can be an exercise in "continuing education"!
On Fri, 2011-12-02 at 21:02 +0000, w8nf wrote:
> I'm glad someone else brought up ESR. That's ultimately what saves the
> design. If the capacitors were zero-loss, then parallleling two caps
> of different values would generate a complete absence of bypassing at
> a frequency inbetween the series resonsnant points of the two
> capacitors. However, due to finite Q of both caps, the in-between
> resonance is damped. The closer together the two capacitors SRFs, the
> more damping is caused by a finite ESR.
6944 2011-12-04 05:05:32 Dean Blake Re: Best Practices for PCBs thanks I learned something on how much better a electrolytic was at higher frequencies..you surprised me!
thanks for the insight..
Date: Sat, 3 Dec 2011 00:47:23 +0000
Subject: [emrfd] Re: Best Practices for PCBs
Hi Dean - I suspect that the single electrolytic on the power pin of the 386 would be quite adequate. Probably unneeded, but available as a precauti
6946 2011-12-04 07:30:47 ehydra Re: Best Practices for PCBs 4nH is 12.5 ohms @500MHz. Now compare this to typical 50 or 100 ohms
input/output stages and you will see the problem. I suggest better
parts, lower parasitic inductance. A transmission line helps because it
decouples areas on the PCB.
As far for the using of "electrolytic": The cap works electrostatic! The
electrolytic is just the contact material on one side of the capacitor
foils. It's function is to dramatically reduce the distance - not
achievable with classic mechanical work.
A 'true' electrolytic capacitor would be a chargable battery like in the
The difference is how matter and electrons shift from one side to the other.
Well, that was the technical suite just for the records.
Dean Blake schrieb:
> thanks I learned something on how much better a electrolytic was at
> higher frequencies..you surprised me! thanks for the insight..
> Hi Dean - I suspect that the single electrolytic on the power pin of
> the 386 would be quite adequate. Probably unneeded, but available as
> a precauti
6947 2011-12-04 17:54:03 boblarkin02 Re: Best Practices for PCBs The context of the comment about electrolytic capacitors was that they have low enough high frequency ESR to produce parallel resonances with small value caps. Sorry if it sounded like I was advocating their use as replacements for ceramics, etc. Bob
6948 2011-12-05 06:19:22 jasonb1963 Re: Best Practices for PCBs How do tantalum capacitors compare with electrolytics for use as RF bypasses? I believe chapter 2 of EMRFD recommends their use when larger values of capacitance are needed, yet effective RF bypass is still required. Published ESR values are down to small fractions of an ohm for the more expensive varieties (ex: Kemet T520V107M006ATE012 100uF tantalum has a published ESR of 12 milliohms).
6960 2011-12-06 06:49:43 ehydra Re: Best Practices for PCBs Tantalum caps work effective like a broadband diplexer for powerline
noise. The switching 'noise' energy is absorbed in the ESR.
If the ESR is too low, you have an oscillator because Q is then high.
This not what is needed.
> How do tantalum capacitors compare with electrolytics for use as RF--
> bypasses? I believe chapter 2 of EMRFD recommends their use when
> larger values of capacitance are needed, yet effective RF bypass is
> still required. Published ESR values are down to small fractions of
> an ohm for the more expensive varieties (ex: Kemet
> T520V107M006ATE012 100uF tantalum has a published ESR of 12
6962 2011-12-06 08:44:32 jasonb1963 Re: Best Practices for PCBs Hi Henry,
I was speaking in the context of using one or more tantalum capacitors of identical values to bypass the power supply in the case where you want to provide a low impedance path to ground for both RF as well as lower frequencies. In such a case, would one not want as low an ESR as possible? I gather from EMRFD that this is a valid method of bypassing, at least on the lower HF bands, but I wanted to better understand the tradeoffs and limitations.
I already gather that it makes sense to use resistors or ferrite beads to isolate the power supply rails of different circuits within a system in order to limit any resonances that may otherwise be introduced when different values/types of capacitors are used for bypassing within individual circuits.
An example of a situati
6963 2011-12-06 09:05:59 Graham / KE9H Re: Best Practices for PCBs Tantalums should NOT be used as bypass caps on a (relatively) unlimited
source. If they are behind a current limited supply such as a linear or
regulator they are OK as power supply bypasses. If it is a high current
as supplied by a lead-acid battery, or a high current AC supply, their
ESR is so low they
can catastrophically fail due to initial inrush current.
Electrolytics with their higher ESR are safe for bypassing high current
If you are dealing with RF and high current rails, as in an RF Power
it is better to use electrolytics in parallel with ceramics, rather than
It is a safety issue, not a performance issue.
--- Graham / KE9H
6965 2011-12-06 13:07:31 jasonb1963 Re: Best Practices for PCBs Hi Graham,
I understand the concern here, but I'm uncomfortable with blanket statements like you make below.
A quick look at the Digikey catalog shows a range of ESRs for Tantalums from a small fraction of an ohm to over 50 ohms. Similarly, a quick look at the ESRs for aluminum electrolytics shows a range of ESRs from a small fraction of an ohm up to some values in the kilohm range. Clearly there is more to it than just the ESR since you can have an electrolytic capacitor with just as low an ESR as a tantalum.
If there is a danger of a capacitor rupturing or even exploding, and it is not a question of exceeding the voltage rating of the capacitor, then the most reasonable explanation is rapid heating while charge flows into the capacitor through its internal resistance which could lead to rupture or explosion due to excessively high internal pressures. Electrolytics would be subject to exactly the same effect, however it may be mitigated by the fact that they are usually physically larger than a tantalum of similar capacity.
If my analysis is correct, then the danger of connecting a capacitor of any type to a voltage source would increase based on the following criteria:
1) Thermal mass of the capacitor (generally correlating with the physical size).
2) Capacitance of the capacitor (smaller values would be incapable of generating significant amounts of heat while charging to anything short of high voltages).
3) DC resistance of the capacitor. I assume this will be related to the ESR of the capacitor and if so, higher ESR values will limit the amount of current that flows inside the capacitor (as you have said) such that any thermal heating that occurs may be safely dissipated by the capacitor before dangerous temperatures are reached.
Based on this I would amend your warning to avoid connecting small high-capacitance tantalums with low ESRs across voltage sources (like the lead acid battery you mention).
If there is something significant I have neglected to consider in this analysis, I look forward to hearing about it.
6966 2011-12-06 15:52:38 Graham / KE9H Re: Best Practices for PCBs Jason:
I stand on what I recommended.
There is a current concentration mechanism in the Tantalums during what is
called a "surge current" or "High inrush current" failure, that does not
in aluminum electrolytics, so it is not a matter of comparing ESRs.
I suggest you Google "surge current" or "High inrush current" failures
in Tantalum caps,
read the following:
Obviously the manufacturers are trying to mitigate the issue, some even
build fuses into tantalums for high rel applications.
Just the messenger, not the expert.
I am aware of companies that have what I recommended as company
wide design policy.
--- Graham / KE9H
6967 2011-12-06 17:10:35 William Carver Re: Best Practices for PCBs I've never heard of a tantalum capacitor "rupturing" or exploding.
You will find explanations that current surges seem to induce a
"avalanche" failure mode that sounds almost semiconductor-ish. Nearby
low-ESR capacitors are quite capable of supplying the current to turn a
weak capacitor into a shorted capacitor. No lead-acid battery required.
But there are other failure modes. It's not one dimensional.
I'd suggest looking in the literature for failure mechanisms of tantalum
capacitors, thermal rating of packages, etc. It's fascinating reading.
6968 2011-12-06 17:44:35 ehydra Re: Best Practices for PCBs Well, if the maximum current to the tantalum can't be controlled, they
have to be avoided. Small impurities in the cap body trigger the
self-destroying process if delta current is too high.
Historically for years the tantalums where the most compact caps
available even for low-temperature working. The alternative was film
caps but lower capacity and higher price too.
This has changed with the newer ceramic types!
A small resistor in front of the tantalum will give some security.
The TPS line is an example of moderate surge-capable tantalum caps.
Graham / KE9H schrieb:
> I stand on what I recommended.
6970 2011-12-06 17:56:36 Dave Re: Best Practices for PCBs I use 10uF ceramics in 0805 and 1206 packages. They are available
for very reasonable prices. I think I saw 100uF ceramic SM caps.
The only problem I have had is in very high gain audio circuits. The
ceramics are microphonic.
Dave - WB6DHW
6971 2011-12-06 19:19:11 jasonb1963 Re: Best Practices for PCBs Hi Graham,
Thank you for the references. I read them with interest. It seems that the mechanism behind the failures is only partially understood based on what I read. However, the AVX paper suggested that it is safe to use tantalum capacitors in low impedance circuits if one or both of the following conditions can be met:
1) 100% testing of the capacitors prior to use.
2) Providing an "adequate" voltage derating.
I am certainly not going to do #1 as I lack the equipment to perform an adequate job. However, I certainly can provide generous voltage deratings if I select tantalum capacitors which could potentially be connected to low impedance voltage sources.
6972 2011-12-06 19:25:00 jasonb1963 Re: Best Practices for PCBs Hi Bill,
"Under some conditions a third stage in the sequence may be initiated by the second. The temperature generated by the electrical discharge could be high enough locally to set off a chemical reaction between the tantalum and manganese dioxide with the liberati
6973 2011-12-06 20:40:39 William Carver Re: Best Practices for PCBs I've been using tantalum capacitors almost exclusively in every
commercial product I designed over a thirty year span. I used CS13
hermetic capacitors starting in the 70s, later AVX SMD tant caps. I'm
still homebrewing on several partial reels of them.
I've never, ever had a failure like that partial quote described. I'll
go look to see what conditions they say could produce that. In fact I've
not had many failures of any kind except where they were installed in
PCB with reversed polarity. Even that didn't do anything catastrophic,
just ruined the capacitor.
The Racal 6790GM has a reputation for having dipped tantalums short,
sometimes taking out PCB traces. But mine hasn't lost one in the four
years I've owned it.
On Wed, 2011-12-07 at 03:24 +0000, jasonb1963 wrote:
> Hi Bill,
> "Under some conditions a third stage in the sequence may be initiated
> by the second. The temperature generated by the electrical discharge
> could be high enough locally to set off a chemical reaction between
> the tantalum and manganese dioxide with the liberati
6974 2011-12-06 22:20:31 William Carver Re: Best Practices for PCBs What you quoted sounds like an end-of-the-world scenario compared to
what Kemet says:
"Capacitor failure may be induced by exceeding the rated conditions of
forward DC voltage, reverse DC voltage, surge voltage, surge current,
power dissipation, or temperature."
"The dominant failure mode is by short-circuit...The dominant failure
mode is by short-circuit....Catastrophic failure occurs as an avalanche
in DC leakage current over a short (millisecond) time span. The failed
capacitor, while called “short-circuited”, may exhibit a DC resistance
of 10 to 104 ohm. If a failed capacitor is in an unprotected low-imped-
ance circuit, continued flow of current through the capacitor may
obviously produce severe overheating. This heat may melt the internal
solder (all Series) and the sealing solder used in hermetic Series."
That's about what I'd expect of anything that's short circuit if there's
no current limiting.
Kemet talks about current surges:
"Heavy surge currents are possible in some applications, however.
Circuit impedance may be very low (below the standard 0.1 ohm/volt) or
there may be driving inductance to cause voltage “ringing.” Surge
current may appear during turn-on of equipment, for example. Failure
rate under current-surge conditions may not be predictable from
conventional life test data. A surge current test is utilized to ensure
against a high frequency of such failures, and a description is
available free of charge. The test has been adopted for all capacitors
under MIL-C-39003/06/09/10 and KEMET’s GR500 specifications".
6975 2011-12-07 06:10:29 jasonb1963 Re: Best Practices for PCBs Hi Bill,
Kemet and AVX are saying more-or-less the same thing. If you read the entire article I quoted, it doesn't sound nearly as bad -- I just excerpted the part about the possibility of burning/exploding. The article does say that this is quite rare.
But if you want to see what *can* happen when a tantalum fails, take a look at the video here: http://www.youtube.com/watch?v=9jDsNe_bmtE
While its true that he causes the tantalum to fail by reversing polarity on it, I believe it induces the same sort of catastrophic failure that is discussed in the AVX article. It is also interesting to note that under these conditions (reverse polarity), the electrolytic capacitor produces by far the most violent explosion.
To summarize, it seems to me that putting some protection diodes (against reverse polarity) and making sure to have at least a 1.25 voltage derating on all of your caps should be effective at reducing any fire/explosi
6976 2011-12-07 08:50:59 William Carver Re: Best Practices for PCBs Aluminum electrolytics have notches on the top so they will explode and
let the steam out gracefully. Maybe.
I have a huge stash of 3A shottkey diodes that I use for reverse
polarity protection at power connection points. If you use split +/-
supplies you have to protect against failures that reverse polarity on
parts, but there has to be a real risk of reverse polarity due to
circuit failure before I'd put reverse protection diodes on every
polarity sensitive capacitor.
On the other hand being close to voltage rating is asking for early
failure with tantalums. I never run them close to their rated voltage.
If for no other reason than I hate "maintenance", hi.
I do have something of a doomsday possibility in a 3KW switcher I'm
making. It runs directly off a 30A 240 VAC circuit with fourteen 560 uF
400 VDC electrolytics intimately in parallel as the energy source for
the MOSFETs. The PCB traces are supplemented with #16 copper bus wires
so the full 200j is available if one fails catastrophically.
450V capacitors would have been better but none were available at a
reasonable price. I satisfied myself with Nichicon 105C capacitors at
85% of rated voltage. I carefully forming them and verified individual
microampere leakage current before putting them in parallel.
There was lots of attention to limiting charging current, "soft start"
is closed loop, only terminating when charging current tapers to a few