Message	Date	From	Subject
13848	2017-05-08 09:13:05	lmeeny	Lead inductance vs. package style
Hello, ACT family logic data sheets indicate no difference in electrical parameters between through hole and SMT packages. I was under the impression that internal chip to pin inductance was lower for SMT parts due to shorted internal connections? Thank you, Ed W2GHD
13849	2017-05-09 23:08:47	Andy	Re: Lead inductance vs. package style
Ed wrote: "ACT family logic data sheets indicate no difference in electrical parameters between through hole and SMT packages." Datasheets are usually min/max, and not necessarily accurate on typ values. Often with a lot of hand-waving too. If the thru-hole number was close enough for SMT, they might not have changed it. "I was under the impression that internal chip to pin inductance was lower for SMT parts due to shorted internal connections?" Shorter, not shorted. Yes. The loop area is smaller -> lower inductance. Usually. At least by a little. Andy
13850	2017-05-10 08:59:33	Dana Myers	Re: Lead inductance vs. package style

Ed wrote: "ACT family logic data sheets indicate no difference in electrical parameters between through hole and SMT packages."

Datasheets are usually min/max, and not necessarily accurate on typ values. Often with a lot of hand-waving too. If the thru-hole number was close enough for SMT, they might not have changed it.

"I was under the impression that internal chip to pin inductance was lower for SMT parts due to shorted internal connections?"

Shorter, not shorted. Yes. The loop area is smaller -> lower inductance. Usually. At least by a little.

Andy