KA7EXM DSP-10 Info/Exchange
PLL Tuneup Procedures

Here is a slightly-different tuneup procedure for getting the PLL's to lock up.   Bob's procedures are really great, but this seemed like a winner.  Note you'll need a frequency counter.

If you are assembling the DSP-10, you may wish to refrain from inserting resistors R106, R54, and the variable resistor R124.  Maybe we can talk Steve into tossing in a couple of extra SMT resistors for the PLL lock procedures.....

(Read everything before doing anything)

Jam-Bit Control Signals

Okay so I'm digressing and we're only on the 2nd paragraph.  First thing is first, if you haven't added a diode in the T/R circuitry, do so now.   It is too easy to accidentially program a sequence that will turn both +10T and +10R signals on simultaneously.  Bob's clever design sends transmit RF back up the receive path in many places, so enabling both transmit and receive will set up some awful loops!  Refer to Bob's web site ("SR105 Diode").  I added a diode from (anode) Q103-Base to (cathode) Q104-Collector.

Run through Bob's UDIAG1 procedure carefully.  His program enables clock, data, serial enable 1 and serial enable 2, each in 5 second steps.  FL1 flashes to tell you which of the four is being toggled.

Take special note of serial_enable_1 and serial_enable_2.  As noted, these two control bits are swapped (incorrectly) in the QST article schematics, so you will want to verify that you wired your DSP-10 up with the corrected sequence:

U107-12 should be controlled by Serial_Enable_2 .  Serial_Enable_1 controls U7 (the 19.68 MHz Synthesizer).  (I think I got that right).

Pardon my going over things that don't seem to have much to do with the PLL;  I burned a month on the serial_enable_1 / serial_enable_2 thing, so I figured it was worth a friendly reminder.  Bob noted the correction, I just didn't re-read the correction the day I was wiring up the 2181 unit.  There's a funny story there actually.

Okay, once you have verified that the four control signals are blipping at their IC's, you can move on.

10 MHz Crystal

Now is a good time to check out the 10 MHz Crystal oscillator on board.  An external 10 MHz reference will be much more accurate / stable, but for now, I'm using the internal rock.  Verify the crystal oscillator oscillates at U7-1 and U104-1 .   With a frequency counter, adjust C110 to obtain 10.0000 MHz.  I added an additional 22pF cap in parallel with C109 & C110.

19.68 MHz Synthesizer

Figure 8 shows the PLL for the 19.68 MHz synthesizer.

Here is a procedure I used to tune up is oscillator.

• Solder a 1" wire on to one end of C78, the blocking cap past U9 .  Clip on a frequency counter here.

• Remove U54, the 47K resistor connecting the PLL's output to the VCO.  Replace this node with a 10K potentiometer.  Straddle the variable resistor between ground and +5V (There is a ground hole near the R54 pad.  Solder a short wire on to the other end of the pot and find a node near the output of U13, the 5V regulator).  The wiper of the potentiometer should be attached to the node R54/C62/L20 .\

• The idea here is you are breaking the loop of the PLL, and driving the local oscillator with your own offset voltage to the varactor.  The varactor D3 will change in value slightly, based upon the amount of DC bias you place upon it.  If everything was operating normally (we had "pll lock,") you would see about 3-4V output from the PLL & U6, which would eventually make it to the varactor.

• Set the potentiometer to 3-4Volts DC.  Examine the frequency of the local oscillator.  Sweep the bias voltage slightly to verify the output voltage varies while you change the bias.  If you aren't tuning around 19.68 MHz within this range, then the circuit will need to be altered slightly.

For my circuit, I added an additional 150pF of cap in parallel with C71 (NP0 leaded part, short leads).  I squeezed L21 slightly, and probably adjusted C69 a little bit.   Main shift came with the change at C71.

Okay, so now you can see 19.68 MHz (give or take) when hovering around 3 to 4 V into the Varactor.  Now remove the potentiometer and replace R54 with a fresh 47K resistor.  Download Bob's UDIAG2 program, which sets this PLL properly.  If all went well, you should see 19.68 MHz on your counter.

126 MHz Synthesizer

The 126 MHz synthesizer is very similar to the 19.68 MHz synthesizer.  I used a similar procedure to get this circuit aligned:

• Solder a 1" wire at C127, the output from the second stage of amplification for the synthesizer.  Attach a frequency counter to this wire.

• Break the PLL loop by removing the 100K resistor, R106.  In a manner similar to the 19.68 MHz procedure, insert your 10k Potentiometer in place of R106 such that the wiper drives the cathodes of the 4 VMMV2101 varactors.  Set the wiper voltage to a little under 4 Volts.

• The frequency counter needs to show 126 MHz or so with this bias voltage.  Sweep the potentiometer up and down to see the frequency vary accordingly.  If you don't see 126 MHz, adjust the reactance in the oscillator accordingly.

• I shortened the length of the slug in L102, as per Bob's suggestion.  In hind sight, I could have skipped this.  Before I was done, I lowered C117 from 10pF to 6.8pF (I had a 7pF 0805 handy from the brickette parts stash).

• Before closing the loop, make sure that varying the slug L102 will indeed give you a little play in the resonant frequency.  In addition, verify that the circuit will continue to resonate clear through the 124.0 to 128.4 MHz range.  This range should be, more or less, centered in the 2.5 to 4ish Volt range.

• Remove the potentiometer and replace R106 with a fresh 100K resistor.  Power up and use Bob's UDIAG2 to program the PLL.  Examine the frequency on the counter (it should be 126.000 MHz).

• To verify the PLL will lock across the whole band, use UDIAG3 to sweep the synthesizer.

Please feel free to send me feedback.

ka7exm at gmail dot com