Here is a slightly-different tuneup procedure for getting the PLL's to lock up. Bob's procedures are really great, but this seemed like a winner. Note you'll need a frequency counter.
If you are assembling the DSP-10, you may wish to refrain from inserting resistors R106, R54, and the variable resistor R124. Maybe we can talk Steve into tossing in a couple of extra SMT resistors for the PLL lock procedures.....
(Read everything before doing anything)
Okay so I'm digressing and we're only on the 2nd paragraph. First thing is first, if you haven't added a diode in the T/R circuitry, do so now. It is too easy to accidentially program a sequence that will turn both +10T and +10R signals on simultaneously. Bob's clever design sends transmit RF back up the receive path in many places, so enabling both transmit and receive will set up some awful loops! Refer to Bob's web site ("SR105 Diode"). I added a diode from (anode) Q103-Base to (cathode) Q104-Collector.
Run through Bob's UDIAG1 procedure carefully. His program enables clock, data, serial enable 1 and serial enable 2, each in 5 second steps. FL1 flashes to tell you which of the four is being toggled.
Take special note of serial_enable_1 and serial_enable_2. As noted, these two control bits are swapped (incorrectly) in the QST article schematics, so you will want to verify that you wired your DSP-10 up with the corrected sequence:
U107-12 should be controlled by Serial_Enable_2 . Serial_Enable_1 controls U7 (the 19.68 MHz Synthesizer). (I think I got that right).
Pardon my going over things that don't seem to have much to do with the PLL; I burned a month on the serial_enable_1 / serial_enable_2 thing, so I figured it was worth a friendly reminder. Bob noted the correction, I just didn't re-read the correction the day I was wiring up the 2181 unit. There's a funny story there actually.
Okay, once you have verified that the four control signals are blipping at their IC's, you can move on.
Now is a good time to check out the 10 MHz Crystal oscillator on board. An external 10 MHz reference will be much more accurate / stable, but for now, I'm using the internal rock. Verify the crystal oscillator oscillates at U7-1 and U104-1 . With a frequency counter, adjust C110 to obtain 10.0000 MHz. I added an additional 22pF cap in parallel with C109 & C110.
Figure 8 shows the PLL for the 19.68 MHz synthesizer.
Here is a procedure I used to tune up is oscillator.
For my circuit, I added an additional 150pF of cap in parallel with C71 (NP0 leaded part, short leads). I squeezed L21 slightly, and probably adjusted C69 a little bit. Main shift came with the change at C71.
Okay, so now you can see 19.68 MHz (give or take) when hovering around 3 to 4 V into the Varactor. Now remove the potentiometer and replace R54 with a fresh 47K resistor. Download Bob's UDIAG2 program, which sets this PLL properly. If all went well, you should see 19.68 MHz on your counter.
The 126 MHz synthesizer is very similar to the 19.68 MHz synthesizer. I used a similar procedure to get this circuit aligned:
Please feel free to send me feedback.
ka7exm at gmail dot com