EMRFD Message Archive 7433
Message Date From Subject 7433 2012-04-25 03:21:44 Ashhar Farhan A pic dds with a pll cleanup
A 16F628 can be programmed to be a dds so that it executes with a
'reference frequency' of 250 KHz as a 32 bit DDS, however, the output
bits will just be 8 bits.
A VCO operating between 8MHz and 25MHz will be divided by a fixed
amount to feed the phase detector while the DDS will be used as a
reference.
The VCO has excellent tuning sensitivity as it is a regular VFO where
the varactors tune a very small part of a segment at any time. The
'bandset' is actually a variable capacitor.
Now, the questions are :
1. Are 8 bits enough for a dds used as a reference to a PLL?
2. What is a good reference frequency range? Lower it is the better is
the dds performance, the higher it is, the better is the PLL
performance.
I tried writing a simulator for this but gave up due to sheer
incompetence with maths. Help!
- Farhan VU2ESE
Tip: never skip laplace tranforms class.
--
Sent from my mobile device7434 2012-04-25 10:32:06 Lasse Re: A pic dds with a pll cleanup
will be 25 MHz means you will multiply reference 1000 times.
Inside the bandwith of your loop filter bandwith... the spectral
behavour of the carrier will be like your reference but 60 dB worse
phase noise and spurs... Using only 8 bits will give plenty of spurs
and this will not be good for your carrier.
You must have a very clean clock to drive your DDS i.e. your PIC, a
cheap computer clock will not be good for spectral purity.
There should be tons of PLL design litterature... and difference between
using a "normal" fixed frequency reference and a DDS is mainly spurious
responses and phase noise.
Just remember, inside the bandwith of your loop filter will reference
dominate and ouside your VCO will dominate the carrier spectrum.
/Lasse SM5GLC
Ashhar Farhan skrev 2012-04-25 12:21:
> I need some inputs ...
> A 16F628 can be programmed to be a dds so that it executes with a
> 'reference frequency' of 250 KHz as a 32 bit DDS, however, the output
> bits will just be 8 bits.
> A VCO operating between 8MHz and 25MHz will be divided by a fixed
> amount to feed the phase detector while the DDS will be used as a
> reference.
> The VCO has excellent tuning sensitivity as it is a regular VFO where
> the varactors tune a very small part of a segment at any time. The
> 'bandset' is actually a variable capacitor.
> Now, the questions are :
> 1. Are 8 bits enough for a dds used as a reference to a PLL?
> 2. What is a good reference frequency range? Lower it is the better is
> the dds performance, the higher it is, the better is the PLL
> performance.
> I tried writing a simulator for this but gave up due to sheer
> incompetence with maths. Help!
> - Farhan VU2ESE
>
> Tip: never skip laplace tranforms class.
>7435 2012-04-25 11:07:02 Tim Re: A pic dds with a pll cleanup
Many of the components are the same as what you suggest (e.g. PIC, PLL, VCO, etc.) but their net result has a remarkable simplicity and covers all the HF ham bands in a downconverting transceiver.
Tim N3QE
7436 2012-04-25 11:24:09 Lasse Re: A pic dds with a pll cleanup
only Elecraft but TenTec, Icom and others.
A neat way of getting resolution from a coarse stepping DDS. It can be a
bit hard to get the same distance between steps, soulds pretty awful if
it is not properly implimented... Still a lot simpler than using a h/b
DDS for reference :)
/Lasse SM5GLC
Tim skrev 2012-04-25 20:07:
> Bucking the suggested trend... look at how the Elecraft K2 does it.
>
> Many of the components are the same as what you suggest (e.g. PIC, PLL, VCO, etc.) but their net result has a remarkable simplicity and covers all the HF ham bands in a downconverting transceiver.
>
> Tim N3QE
>7437 2012-04-25 12:16:59 AD7ZU Re: A pic dds with a pll cleanup
most u-controllers are available with a reasonably fast DAC with adaquate resolution 12bits is common, 16 is available. A software control loop could be designed by using a digital frequency input, then calculate the output voltage required to move or hold the frequency to the desired set point. This scheme would also provide temperature compensation if the frequency measurement was stable.
just a thought
Randy
AD7ZU
7439 2012-04-25 16:16:19 kb1gmx Re: A pic dds with a pll cleanup 7440 2012-04-25 16:18:32 kb1gmx Re: A pic dds with a pll cleanup 7441 2012-04-25 16:31:15 kb1gmx Re: A pic dds with a pll cleanup 7442 2012-04-25 18:43:11 Ashhar Farhan Re: A pic dds with a pll cleanup
Thanks for the insights and suggestions. I have already used an Si570.
It is nice, expensive and tough to get. It works after a fashion :
keep the LO to the higher side of an IF of above 10 MHz. The phase
noise comes up if you push it below 15 MHz.
The MC145170 and other forms of 'PLL+VCXO reference' breed need a VCO
that is bandswitched. K2 does that with a number of latching relays -
Not an option in these parts of the world.
My inspiration comes from chris trask's dds that used regular TTL chips.
I am now considering the arduino. It gives me 20 MIPS with 16 bit
operations. I should be able to add two 32 bit numbers, waveform them
and push out 12 bits in around a microsecond. External latches should
be easy with 74ALSxxx parts clocked externally by a D-Flipflop.
Btw, if we consider an 8 bit divider (from two 74HC192s) that divides
the HF VCO to a 100KHz reference, the DDS has to tune just +/- 2KHz to
tune the entire range. This means, I could use a narrow bandpass
filter at the output of DDS. Makes sense?
- Farhan
7443 2012-04-26 03:29:18 Juanjo Pastor Re: A pic dds with a pll cleanup
4-5 MHz (say an AD9834, by example) as the reference for a PLL. The DDS will
have tiny steps, not audible, and almost perfecty stable frequency being use
as variable reference for the PLL stabilizing the hi freq VCO. That approach
is used in commercial equipment and even in some kits like the Tramp of
QRPproject.
If the phase detector can be driven by square signals, using the 16F628 as a
NCO and squaring the divided signal of the VCO, maybe that would be an
interesting setup, too. But I am no engineer, so engineers around could
indulge better in the idea.
73, 72 de Juanjo, EC5ACA. EA-QRP #104, G-QRP #9742, QRP-L #1662,
FP #899.
Juanjo Pastor
C/San Roque, 4-1º
46460 Silla
SPAIN
----- Original Message -----
7444 2012-04-26 04:29:58 Ashhar Farhan Re: A pic dds with a pll cleanup
jitter. Instead, the sine out is passed through a narrow band pass
filter (some times made out of crystals). This signal is then driven
to clipping to get a square wave.
I am just trying to understand if a simpler and more discrete design
could replace a standard dds chips. My instrumentation is primitive
and I still don't have a specan up and running. Hence asking around
before building the design. Maybe I should just build it and discuss
the results...
- Farhan
On 4/26/12, Juanjo Pastor <ec5aca@wanadoo.es> wrote:
> One typical answer is to use a moderate frequency DDS like one working at
> 4-5 MHz (say an AD9834, by example) as the reference for a PLL. The DDS will
>
> have tiny steps, not audible, and almost perfecty stable frequency being use
>
> as variable reference for the PLL stabilizing the hi freq VCO. That approach
>
> is used in commercial equipment and even in some kits like the Tramp of
> QRPproject.
>
> If the phase detector can be driven by square signals, using the 16F628 as a
>
> NCO and squaring the divided signal of the VCO, maybe that would be an
> interesting setup, too. But I am no engineer, so engineers around could
> indulge better in the idea.
>
> 73, 72 de Juanjo, EC5ACA. EA-QRP #104, G-QRP #9742, QRP-L #1662,
> FP #899.
>
> Juanjo Pastor
> C/San Roque, 4-1º
> 46460 Silla
> SPAIN
>
>
> ----- Original Message -----
>7445 2012-04-26 07:05:56 William Carver Re: A pic dds with a pll cleanup
Ulrich Rohde described a synthesizer that generated an up-conversion LO,
75-105 MHz. It used an 8-bit AD7008 DDS to generate 10.7 MHz, filtered
by a 10 KHz wide xtal filter to strip off most spurs, as the reference
for an MC145170 which has programmable N and R dividers.
The mathematics behind it is "Euclid's method" of finding the greatest
common divisor of two integers. There was a small gap in the general
coverage that he did not mention but the concept was OK. NOTE, however,
in general you can only closely APPROXIMATE a specific output
frequency.
Euclid's iterative method of choosing N and R for the PLL requires a lot
of computing power or a huge ROM lookup table. Today maybe it could be
done in a DSP-oriented micro.
DDS chips, by virtue of higher clock frequencies and more bits in the
phase accumulator and DAC, are much much much cleaner than the AD7008.
And have more resolution. Look at Ulrich's phase noise numbers. For 1995
the performance was pretty good, especially covering 75-105 MHz in a
single VCO.
Today it could be improved somewhat with a cleaner DDS, wider 10.7 MHz
filter and wider loop bandwidth. But it can't compete with the close in
phase noise of PA3AKE's 9-39 MHz down conversion LO using an AD9910
clocked at 1 GHz!
W7AAZ7446 2012-04-26 10:08:57 Ashhar Farhan Re: A pic dds with a pll cleanup
On 4/26/12, William Carver <bcarver@safelink.net> wrote:
> "A High Performance Hybrid Frequency Synthesizer" in March 1995 QST by
> Ulrich Rohde described a synthesizer that generated an up-conversion LO,
> 75-105 MHz. It used an 8-bit AD7008 DDS to generate 10.7 MHz, filtered
> by a 10 KHz wide xtal filter to strip off most spurs, as the reference
> for an MC145170 which has programmable N and R dividers.
>
> The mathematics behind it is "Euclid's method" of finding the greatest
> common divisor of two integers. There was a small gap in the general
> coverage that he did not mention but the concept was OK. NOTE, however,
> in general you can only closely APPROXIMATE a specific output
> frequency.
>
> Euclid's iterative method of choosing N and R for the PLL requires a lot
> of computing power or a huge ROM lookup table. Today maybe it could be
> done in a DSP-oriented micro.
>
> DDS chips, by virtue of higher clock frequencies and more bits in the
> phase accumulator and DAC, are much much much cleaner than the AD7008.
> And have more resolution. Look at Ulrich's phase noise numbers. For 1995
> the performance was pretty good, especially covering 75-105 MHz in a
> single VCO.
>
> Today it could be improved somewhat with a cleaner DDS, wider 10.7 MHz
> filter and wider loop bandwidth. But it can't compete with the close in
> phase noise of PA3AKE's 9-39 MHz down conversion LO using an AD9910
> clocked at 1 GHz!
>
> W7AAZ
>
>
>
--
Sent from my mobile device7447 2012-04-26 10:14:13 Tim Re: A pic dds with a pll cleanup 7448 2012-04-26 15:38:17 kb1gmx Re: A pic dds with a pll cleanup 7449 2012-04-26 21:25:23 Ashhar Farhan Re: A pic dds with a pll cleanup
The latching relays are available, but at a pretty high cost. The
regular relays are a bad idea anywhere near a vfo. On the other hand
electronic switching (with diodes) can lead to the diodes being turned
on the vfo's own high energy, this has caused untold misery in the
past.
Let me explain my proposed topology. We begin with a traditional vfo
tuned with a nice variable capacitor that can span, let's say, X to 25
MHz. Then we add a fine tuning mechanism with two varactors that can
tune over a 200 KHz segment. The user sets the band with the tuning
cap and an 16F628 measure the frequency and accoringly sets a pair of
74LS192s to divide down to approximately 100 KHz. At this time, the
DDS starts to drive the PLL and we obtain phase lock. The
voltage/frequency sensitivity is great as the varactors tune over a
very small part of the band. The phase noise of the vco is still nice
due to restricted tuning range. The dds output can be filtered to a
bandpass of+/-3KHz at 100 KHz that drives the Phase detector. I am not
sure of how many bits of dds output resolution will be good to have.
In such a setup. Ordinarily, I would just build it and measured. I
lack instrumentation to measure spectral output. Apart from the other
considerations, there must be a away to do away with switching
complexities and discover a 'beautiful' way to achieve the noise free
stable local oscillators for our kind of radio work.
- Farhan
7450 2012-04-26 23:19:33 Ashhar Farhan Re: A pic dds with a pll cleanup
I misunderstood your comment. Let me illustrate what I was suggesting.
Consider a DDS with 32 bit accumulator but only 1 bit resolution. The
output will go high and low whenever the accumulator crosses zero.
However, the zero crossing are latched to the output of the dds only
on the edge of reference clock. Hence, the square wave output will be
jittery straight out of the 1-bit output dds.
Oth, if we take a sinewave output froma dds, we won't get a zero
crossing at the precise edge of the clock. A way to acheive that is by
smoothing out the dds output so that the rate of change of voltage
between two samples is as close to the desired output as possible.
This we do by a bandpass filter. Then, we can use a limiter to detect
the zero-crossings and convert the output to a square wave. This
square wave will have far less jitter than the earlier method.
Sorry for the confusion. Can you share some circuit details? I'd love
to study it.
- Farhan
7451 2012-04-27 22:39:02 Tim Re: A pic dds with a pll cleanup
In particular, maybe you want a FLL (Frequency Locked Loop) ala
http://www.9h1lo.net/fll/fll.pdf
or
PA0KSB's Huff N' Puff, ala EMRFD 4.6/4.7
Both start with a basic LC VFO and add frequency stabilization via simple logic or a PIC and a crystal reference.
It is not a DC-to-daylight solution like you occasionally seem to be giving as a goal. In particular a Huff-N-Puff base LC VFO has a span of a few hundred kHz in a ham band, and the fine tuning has a very limited range used only to stabilize the unit. (Usually the range is so small that the varactor characteristics of the LC oscillator's transistor junction gives more than enough range.) But it is simple and sweet and works oh so wonderfully7452 2012-04-27 22:55:33 kb1gmx Re: A pic dds with a pll cleanup 7453 2012-04-27 23:03:12 kb1gmx Re: A pic dds with a pll cleanup 7454 2012-04-28 08:41:27 William Carver Re: A pic dds with a pll cleanup
> order bit from the phase accumulator as it represents the Sign of the
> wave form and is regular around 180 degress or in analog term the zero
> crossing. It has jitter equivilent to the clock driving the latches in
> the phase accumulator. Since that is usually a decent crystal source
> I'd expect low jitter. It is also the right thing to drive
> a digital phase detector.
number being added divides evenly into the 32 bits, the number of
additions to produce both half scale (setting MSB of the accumulator)
and to overflow (clearing MSB of the accumulator) won't always be the
same. This leads to a variation in the number of additions (clock ticks)
to overflow.
For example, assume the phase accumulator is 4 bits. Full scale is 31d.
Lets say the phase increment is 5d.
Starting from zero, the phase accumulator contents will be 5, 10, 15, 20
25, 30. The next tick it overflows, losing the MSB, and the sum in the
phase accumulator is 3.
So in fact the sequence will be 20, 25, 30, 3, 8, 13, 18, 23, 28. The
next tick it overflows, again losing the MSB, and now LSB sum becomes
1.
So the sequence continues as 18, 23, 28, 1, 6, 11, 16,
ETC.
>From a practical standpoint if the phase increment evenly divides intothe accumulator you DO get a perfect square wave, and a wonderfully
clean DDS output. Very low spurs. But for those phase increments you
don't need a DDS, a digital counter will do the same thing!
When it doesn't divide evenly, which is virtually all of the time with
32 or 48 bit phase accumulators, then in analog terms we can think if it
as a low frequency "beat note" in the output. A phase modulation of the
output. PM that creates sidebands. Or, in DDS parlance, spurious.
More bits in the phase accumulator reduces the frequency of overflows,
producing lower frequency PM and this reduces the amplitude of the
spurs. A little.
W7AAZ7455 2012-04-28 13:20:29 kb1gmx Re: A pic dds with a pll cleanup 7456 2012-04-29 14:04:28 William Carver Re: A pic dds with a pll cleanup
In my proposed 5-bit phase accumulator, to which 5 is being added, I
worked out the modulo-32 sums from each clock tick as follows (with the
columns adjusted to the 0-->1 edge transitions) :
I've aligned the MSB edges of the addition of a phase increment of 5 to
a five-bit (31=full scale) phase accumulator that started with zero:
0 (-MSB EDGE), 5, 10, 15 , 20 (+MSB EDGE), 25, 30
3 (-MSB EDGE), 8, 13, 18 (+MSB EDGE) , 23 , 28
1 (-MSB EDGE), 6, 11, 16 (+MSB EDGE) , 21 , 26, 31
4 (-MSB EDGE), 9, 14, 19 (+MSB EDGE) , 24 , 29
2 (-MSB EDGE), 7, 12, 17 (+MSB EDGE) , 22 , 27
This 32-tick pattern repeats (27 + 5 = 32 = 0 modulo-32)
0 (-MSB EDGE), 5, 10, 15 , 20 (+MSB EDGE), 25, 30
3 (-MSB EDGE), 8, 13, 18 (+MSB EDGE) , 23 , 28
1 (-MSB EDGE), 6, 11, 16 (+MSB EDGE) , 21 , 26, 31
4 (-MSB EDGE), 9, 14, 19 (+MSB EDGE) , 24 , 29
2 (-MSB EDGE), 7, 12, 17 (+MSB EDGE) , 22 , 27
Five lines show the repeating pattern of the phase accumulator.
In 32 clock ticks, four times the 0-->1 transition of the MSB takes
THREE clock ticks. Once it takes FOUR clock ticks. The 0-->1 edge is
jittering by one clock tick. Even if the clock is a perfect 1 MHz with
no jitter there is a 1 uS jitter in the transitions of the MSB of the
phase accumulator.
Lets say the clock is 1 MHz. If the 5-bit phase accumulator is connected
to a 5-bit DAC and a brick wall <500 KHz lowpass filter, will the
resulting analog signal be a sine wave of 5/32 * 1 MHz = 156.25 MHz?
Bill W7AAZ7457 2012-04-29 14:55:08 kb1gmx Re: A pic dds with a pll cleanup 7458 2012-04-29 15:46:16 William Carver Re: A pic dds with a pll cleanup
product in the mid 1980s and currently an AD9912 clocked at 1 GHz.
I understand that the 5-bit accumulator isn't a practical number. It was
just a simple example that shows, in my mind, that jitter DOES exist in
the logic transitions of the most significant bit of the phase
accumulator.
Bill7459 2012-04-29 17:16:57 kb1gmx Re: A pic dds with a pll cleanup 7460 2012-04-29 18:49:43 William Carver Re: A pic dds with a pll cleanup
What I am saying is the MSB is not symmetrical, its edges are shifting
by one clock time. Knowing the phase increment and accumulator size it
is predictable, albeit only easily seen using small numbers as in my
example.
It is phase modulation, it results in discrete "PM spurs" not the same
as phase noise caused by a noisy clock or power supply noise. If you
don't want to call it jitter, OK. But the changing edge time is there
and the output is not symmetrical except in a very, very few cases.
Bill7461 2012-04-29 22:23:57 William Carver Re: A pic dds with a pll cleanup
to edges is not stable unless the phase increment is one of the few that
divide into the phase accumulator bits without a remainder
(2,4,8,16,...).
The Analog Devices white paper you referenced earlier says so, and
figure 10 of that paper shows the phase modulation spurs which are the
result for the usual case where there is a remainder.
I was really excited building a 48 bit AD9912, thinking the spurs at 30+
MHz would be much than the AD9910 which has a 32 bit phase accumulator.
Martein Bakker had already built both and reported the spur and phase
noise levels were virtually identical.
No point in continuing this since neither one of us is budging, hi.
Going back and forth with email is too slow to converge.
Bill7464 2012-04-30 08:38:20 Tim Re: A pic dds with a pll cleanup
My consolation was that by shifting the tuning word just an eensy bit (fraction of a Hz) the spurs could often be removed or at least moved so far out of band that they didn't bother my ears anymore. I tried to automatically do this spur-shifting (and I think even AD publishes an app note on avoiding "tuning words of evil") but was not succesful.
"Squaring the circle" (converting sine to a square wave and then back) seems appealing sometimes but I've never found it to help. When I tried it, it introduced all sorts of "fuzzies" that came and went as I turned the tuning knob, I think I was hearing VHF FM stations7467 2012-04-30 10:54:15 William Carver Re: A pic dds with a pll cleanup
spurs, hi. But superhet spurs are countable, while the number of PM
spurs that a DDS can generate is mind numbing.
The very first DDS article in QST, back in the 80s (AS-logic DDS,
clocked at 16.777216 MHz) didn't mention spurs. When I used 5.0-5.5 MHz
as a remote VFO for my TR-7A was astoundingly dirty with phase
modulation (PM) spurs everywhere. Definitely DID NOT transmit with it!
DDS has come a long way in the several-decades since that discrete DDS
article. I clock an AD9951 at 538.8709 MHz (for which 8 LSB =
1.000000000 Hz) to generate 160-10m LO downconverting to a 5.2 MHz IF
and there are only a few detectable PM spurs per band.
Martein Bakker, PA3AKE, says the AD9910-12, clocked at 1 GHz, are about
6 dB better than the AD9951 clocked at 1/2 GHz and almost has "no
detectable spurs". He's done an incredible sleuthing job to nail all the
possible noise sources...power supply regulator noises, squeeky-clean 1
GHz clock, so I'm using his hardware design.
But software can do the best hardware in. One thing is to make sure your
output range(s) does not tune over a submultiple of the DDS clock (1/3,
1/4, 1/5, etc). That's deadly. Next, not some rational (N/M) ratio of
the clock frequency where N and M are small numbers. For example, 3/4 or
3/8. The further away from a ratio of small numbers the cleaner the DDS
becomes.
Finding bad choices would be tedious, but Euclid's method of finding the
greatest common divisor of two integers can be used to evaluate a DDS
clock and output frequency to see if there is one of those nasty small
ratios between them. This is the same math that lets you evaluate the
coverage of a DDS-referenced PLL with adjustable reference and
adjustable VCO divisors. Eldon Eller, an extremely bright English major,
taught me Euclid's method about 30 years ago.
The latest DDS nasty that popped up is AM noise from the bandgap DAC
reference of the AD9910 and AD9912. The AD9951 and earlier DDS chips
have a bypass pin for that reference, and a big capacitor gets rid of
the several-hundred-KHz wide AM noise pedestal. But Analog Devices, in
their infinite wisdom (???) does not bring that point out on either the
AD9910 or AD9912.
So the latest-greatest DDS chips have AM noise which is about 20 dB
higher than the PM noise. Looks like somebody dropped the ball, big
time. AD, conveniently, does not specify the AM noise. You cannot ignore
the AM noise of the 1 GHz chips.
Unlike PM noise/spurs, which you are stuck with, AM noise can be
suppressed by clipping the output. Experimentally a Tiny Logic inverter
suppressed AM noise by about 20 dB up to 100 MHz. But if you use
discrete filtering to clean up the DDS you have to filter again after
the squaring. And all they had to do was bring out the bandgap reference
like they'd been doing for decades. Go figger.
Bill - W7AAZ7468 2012-04-30 15:51:27 kb1gmx Re: A pic dds with a pll cleanup 7469 2012-04-30 16:12:38 William Carver Re: A pic dds with a pll cleanup
about it. Everything else is there just to tune that VCO.
When you look at the phase noise floors of almost all of the commercial
rigs you have to wonder where the wonders of DDS went. I guess it's all
expended in "agility", "memories" and other peripheral issues, while
spectral purity has disappeared. It blows my mind to see rigs with -130
dBc/Hz noise at 100 KHz away from the carrier.
But, as with a lot of things, the manhours and dollars to actually get
the full measure of DDS promise is high, and the manufacturers focus is
on dollar return from hood ornament "features" rather the solid basic
performance. Their customers are not well informed...for whatever reason
the radio media writes flowery "reviews" about how the menus are
accessed and similar total BS, and not one word about transmit third
order IMD that's less than 20 dB below one tone or the wideband noise
floor being transmitted as well as received.
I'm glad to read that alternatives are being pursued on [emrfd] and a
few other sites and know that we're not all brain dead.......
Bill
7470 2012-04-30 16:15:48 Nick Kennedy Re: A pic dds with a pll cleanup
the 86 and 87 ARRL Handbooks. Wire wrapped the whole thing. I did transmit
with mine, on my Ten Tec Corsair. I plead ignorance.
It had discrete phase adder chips, a sine wave on a PROM and a discrete
DAC. I spent an infinite number of hobby hours programming up a DOS based
control program with RIT / XIT, memories, scan, etc, all in '8086
assembler. Plus added an optical encoder. Fun.
73-
Nick, WA5BDU
7471 2012-04-30 16:21:50 William Carver Re: A pic dds with a pll cleanup
>I didn't have an antenna at that time Nick, or I probably would have put
> Yep, I built one too. It was from QST April 84 and February 85 and
> also the 86 and 87 ARRL Handbooks. Wire wrapped the whole thing. I did
> transmit with mine, on my Ten Tec Corsair. I plead ignorance.
it on the air, too!
And having exposure to the sampling theorum and not much else, I was not
equipped to expect the kind of spurs that board generated. Now you would
think the author, or the ARRL Lab that MUST test all construction
articles, wouild have at least put a tiny little comment in there,
wouldn't you??
Bill7475 2012-05-01 07:07:12 Juanjo Pastor Re: A pic dds with a pll cleanup
What is the advantage of using a low frequency DDS as the reference for a
PLL? The dual loop PLL thing has catched my eye, will make an internet
search. TIA.
73, 72 de Juanjo, EC5ACA. EA-QRP #104, G-QRP #9742, QRP-L #1662,
FP #899.
Juanjo Pastor
C/San Roque, 4-1º
46460 Silla
SPAIN
Tel.: +034 96 120 17 67
Movil: 651 35 35 117478 2012-05-01 12:56:50 William Carver Re: A pic dds with a pll cleanup
frequencies. If you vary the reference now you can fill in between those
discrete steps.
For example if you use a 10 KHz reference to generate 1.8-30 MHz, and
you can move that 10 KHz by just 55.55555....Hz, you can obtain ANY
output frequency.
A DDS has uncountable spurs, most of which are far from the carrier. So
a PLL will strip off those who are spaced more that the PLL loop
bandwidth. Unfortunately those that are close to the carrier will not be
removed and will appear as spurs on the VCO.
Ulrich Rohde's article in QST described using a 10.7 MHz DDS, filtered
by a narrow FM filter, as a reference for a PLL where both dividers to
the phase detector could be changed. This is intellectually
interesting.
Unfortunately the tuning step size varies because the reference divisor
is changing so it provides continuous coverage and stability, but
producing even an approximation to fixed step size in real time (as you
spin a knob) requires a lot of computing power.
W7AAZ7479 2012-05-01 15:30:02 kb1gmx Re: A pic dds with a pll cleanup