EMRFD Message Archive 6815
Message Date From Subject 6815 2011-11-10 21:52:35 jasonb1963 Update on FLL Experiment I put together a not-very-stable VCO circuit for 40M this evening. I then hooked it up to the CPLD-based FLL and tried many things. In the end, I was able to stabilize the frequency to about +/- 3 Hertz, although if the VCO is exposed to a draft of cold or warm air, it will deviate more before correcting.
I tried two different loop filters. The first was a simple integrator and ultimately worked the best. The second was a second order active chebychev low pass filter.
The loop filter drives a MV2101 varactor which is connected to the resonator via a 12pF capacitor.
The output of the CPLD is one of two logic values (0 or 3.3 volts) depending on whether the frequency is off high or off low. I tried a high impedance output if the count matched exactly but it didn't seem to offer any benefit and used a few more gates on the CPLD.
Enough of this signal got through the low pass filter to cause audible modulation of the VCO output. I experimented with cutoff frequencies between about 0.025 and 1 Hertz. I was able to improve the result somewhat by decreasing the gate period to 1ms for the counter on the CPLD, resulting in a shorter interval between output pulses, but I was ultimately not satisfied with the result because I could still hear the modulation on the carrier. I tried gate periods between 1ms and 100ms. Given the high impedances used in the filter and the proximity to the CPLD and the VCO, it's likely that stray coupling was a contributing factor as well and better results could be obtained with careful shielding. I may try that next.
The integrator produced more satisfying, but still imperfect results. With 100ms gate periods, it was possible to hear a slight periodic wavering of the output signal when the FLL makes corrections. With shorter gate periods, I detected weak, but audible modulation when I monitored the output on a receiver. Setting the integrator RC time constant to 100 seemed to produce the best results (1M resistor and 100uF capacitor!) with a 100ms gate time. This resulted in the +/- 3 Hertz short-term variation as measured on my frequency counter.
At one point I walked away from the circuit for over an hour and when I came back the VCO was still locked despite being in a drafty unheated room. It can, however, become unlocked as I discovered when manually adjusting the frequency while the FLL was locked and the output of the integrator became pinned to it's maximum value and could not rise further. However, if the user sets the frequency when the loop filter output is in the middle of it's adjustment range, there are thousands of Hertz of adjustment range on both sides of the set frequency (depending on exact circuit values chosen, of course).
I suspect that if I rebuild everything with shielding and isolation between the different sections of the circuit, the performance will be much improved. I was just looking for some proof of concept tonight, and I think I got it.
Another thing I'd like to try is the n-bit output values I mentioned in a previous posting, but that will have to wait for another CPLD with more logic gates on it since the one I'm using now is maxed out. Rather than working with a 1-bit output, the CPLD can output an n-bit value which can be fed to a DAC which then drives the loop filter. This will allow the system to provide greater correction in the event the frequency is far off and small correction when the frequency is barely off. I'm hoping it will reduce the slight wavering sound I experienced with today's setup.
If anyone else is interested in trying this out for themselves, I can upload the VHDL and/or provide schematics or block diagrams of what I've done so far. If you're handy with ugly bug construction and good shielding practices, I expect your results will be better than mine.
If anyone has a background in control theory, perhaps you can comment on the value of trying a combination of a low-pass filtered output and integrator output combined and fed to the varactor?
By the way, I measured phase noise at -115dBc with a banged up old Tektronix 2755 spectrum analyzer 10KHz away from the carrier. I gather this isn't very good for a VFO though it may be degraded by the lack of shielding and some noise on the power rail which I couldn't get rid of.
6816 2011-11-11 08:19:26 Alex P Re: Update on FLL Experiment A few years ago, built several variations of a 10 MHz vfo with a Huff-Puff FLL using a similar circuit as what your trying but without the CPLD. Used J309s as the osc and source follower output. Although the control loop worked very well over the short term and over a limited freq range, the temperature generated (or absorbed) on most all the analog components would cause sufficient medium/long term drift as to go beyond the range of the Huff-Puff/integrator control loop. The drift characteristics were exacerbated by the ambient temperature variation. Multiple experiments were performed which included shielding, housing the circuit in a thermostatically controlled and insulated enclosure.
Even changing the vfo coil winding to relatively exotic metals with low thermal coefficient of thermal expansion didn't do much. BTW shining light on the varactor showed a measurable freq change. Some of the findings that I remember were that the system worked acceptably well at lower than about 4-5 MHz but still had long term and ambient temperature drift, although less drift than at 10 MHz. Using an air dielectric variable capacitor with dual low capacitance varactors increased stability somewhat. Reducing the power to the J309's and hence the thermal dissipati
6819 2011-11-11 16:42:38 jasonb1963 Re: Update on FLL Experiment Hi Alex,
Thanks for replying. It is nice to hear about your experiences with this concept. You don't say what you were using on the digital side of things and I would be curious to compare your control system with mine.
The best success I have had with VFOs so far is with a NRO configuration I found in EMRFD, using a pair of J310s. There are some tricks people use to stabilize the VFOs against temperature drift using components with known temperature coefficients to counter some of the effects of drift, but I'll be the first to admit to not having tried very hard to stabilize any of the VFOs I built since I was generally connecting them up to a PLL so it didn't matter.
The limiting factor for lock range with my design is the change in frequency the varactor diode which is connected to the FLL is capable of providing. This in turn is affected by the tuning voltage range the loop filter is capable of putting on the varactor diode.
(stepping out to my lab to take a few measurements).
OK, Kvco is about 2KHz/volt with my current setup. That gives a tuning/lock range of +/- 4Khz in my 5V system (with 1V as a minimum). Now, I don't know what to expect from a decent VFO, but I would hope that the variation would be well under this over any reasonable temperature range.
If, however, a greater lock range is needed, the coupling capacitor between the varactor diode and the resonator of the VFO can be increased. The downside to this is that it will magnify the effect the digital tuning signal has in producing undesired modulation of the carrier. I've considered a couple of approaches to counter this effect while retaining the increased tuning range.
One enhanced approach I just began exploring today involves having the FLL output more than 1 bit of tuning signal. With this method, the tuning range could be significantly increased since once the VFO was close to the locked frequency, only the LSB of the tuning signal would be active and its amplitude could be small enough to avoid any objectionable modulation of the carrier. I'm struggling to make this code fit on the current CPLD I'm working with, although I did manage to get it up to 2-bits of output with some tweaking and may even be able to get it up to 3-bits before being forced to move to a larger CPLD (which is currently on order and should arrive next week since I had to learn how to solder a 0.5mm TQFP-100 by ruining the one I already had!).
The other approach I've considered is to retain the 1-bit output but pulse width modulate it (on the CPLD) with a duty cycle proportional to the amount by which the frequency is off. The logic to do this won't fit
6820 2011-11-12 15:04:40 kb1gmx Re: Update on FLL Experiment 6822 2011-11-14 09:32:00 Alex P Re: Update on FLL Experiment Allison and Jason,
Allison, concur with the additional inputs you wrote.
Many of the papers I've read on the Huff-Puff control loop say that you need a relatively 'stable' vfo to begin with so as to not go beyond the compensation range of the control loop. This was my experience also. The control loop in my vfo included a simple 74HC74 architecture based on the "2-chip vfo + Huff Puff" by Hans Summers but instead of a digital 3 MHz vfo implemented as IC2b in the article, I used the output of IC2a to control the varactors of my 10 MHz vfo.
Jason's CPLD architecture is interesting and look forward to the results.
Allison, maybe I'm misunderstanding what you wrote regarding the great drift results of your 14 MHz vfo. I interpret these results as being for a tube version vfo versus a fet version that Jason and I are discussing.
Could you kindly confirm that these drift results are for a tube design or otherwise? Also, are you using any varactors at all or only an air variable cap to tune it? and what is the frequency range of it?
In one version of my 10 MHz fet design, the temperature drift compensation was implemented with the usual capacitor compensation methods as you mentioned in your post. Couldn't quite get the compensation needed in the limited amount of time available to play with the thing. However,in addition, a complicating factor was the varactor sensitivity to heat as well as the heat effects to the J309's (presumably and asssuming junction effects) at this higher (10MHz) frequency. Reducing the operational frequency showed a reduction in drift effects.
As an alternate and additional version, opted to try to find those special variable temp coefficient compensati
6823 2011-11-14 15:10:51 NeilDouglas Re: Update on FLL Experiment Alex,
The variable temperature coefficient trimmer was called a tempatrimmer made
by Oxley in the U.K.
They are no longer manufactured
6824 2011-11-14 18:29:39 William Carver Re: Update on FLL Experiment Tempatrimmer is gone. Expensive, but companct, and in production this
allowed adjustment of temperature compensation without soldering, and in
If you have a differential variable capacitor it can be used to create
an adjustable temp coefficient tank: put fixed capacitors from the VFO
to each side of the differential trimmer: one probably NPO, the other
N750. If they're same value and well matched you can dial in temperature
compensation fairly quickly.
Differential capacitors aren't real common. E.F. Johnson, for one, made
It's not as elegant, but you can approach the same thing with two
independent trimmers, one in series with the NPO and the other in series
with the N750 capacitor: it's up to you to increase one and decrease the
other to keep total tank capacitance more-or-less unchanged, as you
change the temperature coefficient. I've not tried that, but it
shouldn't be too difficult.
The usual method is putting the VFO and/out of the freezer with power
wires and RG174 so you can monitor the frequency as you change the
compensation. You won't get "instant gratification"s since it takes many
hours for an oscillator to recover from soldering on its tank. It takes
many attempts and tweeks to get the right compensation, but it can be
done. I kept a yellow tablet on the kitchen counter, got baseline in the
morning, came home from work at noon to put it in the freezer, checked
it at night. After about a week I had a 2.2 MHz VFO with 4434 European
color burst xtal filter that's is a very, very temperature stable 40m
mobile CW rig.
6825 2011-11-14 18:35:49 Alex P Re: Update on FLL Experiment Neil,
Thanks for the input.
I wonder if there is any info on how they work...any pictures or drawings? I seem to remember that they looked like piston trimmers.
6826 2011-11-14 18:42:37 Alex P Re: Update on FLL Experiment Thanks for the workaround solutions... A lot better than successively soldering in caps.
6827 2011-11-15 00:14:25 NeilDouglas Re: Update on FLL Experiment Alex,
This ad has a picture of one.
It looks like it's based on a differential capacitor.
You can still get Jackson differential trimmers from
You could then connect equal value capacitors to either side, a NPO to one
side and N750ppm to the other.
As W7AAZ suggests it would be cheaper to use two normal trimmers.
6835 2011-11-16 22:49:08 jasonb1963 Re: Update on FLL Experiment I've done some more work with the frequency locked loop (FLL) and thought I'd share it here as I feel I may be getting close to some conclusions.
I got a larger CPLD and wrote some VHDL that implements a 6-digit frequency counter with 10Hz resolution as well as the frequency control loop all in one. It isn't necessary to have more resolution with the frequency counter, and here's why:
The counter is completely synchronous. It continuously counts each cycle of the input. The counter is reset each gating period. But since the gate clock is asynchronous with the VCO input, there is a fraction of a period which winds up being counted in the next gate cycle.
If you are trying to lock to 1.000000 MHz, but the true frequency is currently 1.000002 MHz, the counter will read 1.00000 MHz on 4 out of 5 gate periods, and 1.00001 MHz on 1 out of 5 periods. This is because the fraction of the input frequency timing period adds up over the course of 5 gating periods (500 ms) with the result that on every fifth period, the count his higher by one (the fractional phases are adding together). The result is that the frequency is nudged downwards despite the apparent lack of sufficient resolution. In theory, this should work with even lower resolutions as well.
So with my current setup, I get 2 bits of correction every 100ms, depending on how far off the frequency is. If it's off by 50Hz or more, I turn on the most significant bit, otherwise the least significant bit is used for steering the frequency. If the difference is zero, no input is applied to the loop filter. This is done with a simple op-amp summing circuit connected ahead of the integrator (loop filter) and separated by a CMOS switch (74HC4066) which is turned off whenever the frequency difference is zero.
Now at this point I should probably be creating a mathematical model of the entire loop in order to understand the theoretical limits of its performance, but I'm putting that off for now. Instead, I've made several observations of the performance of the loop.
First, it was necessary to adjust the coupling capacitor and gain of the summing stage so that the low order bit of the output steered the frequency slowly, and the high order bit more quickly. I settled on a 3:1 steering ratio for now.
Next, some experimenting with the loop filter was necessary. As I mentioned, the loop filter is an integrator. I assumed that if I set the time constant of the loop filter too low, the steering voltage would change too quickly and wind up oscillating about the lock frequency. And if I set it too high, it would take a longer to respond, but oscillate less.
It looks like I was wrong. I suppose this is where the mathematical model would have saved me the effort. But as far as I can tell, if you don't have a reasonably stable VFO, you can expect the steering voltage will overcorrect in one direction, then reverse and overcorrect in the other direction. The frequency of this oscillation is controlled by the time constant of the integrator.
I would have thought that longer time constants would have resulted in less overshoot than shorter ones, but this does not seem to be the case. It looks like the integrator has an effect a lot like momentum and mass so that by giving it a long time constant, the correction pulses from the CPLD take longer to have an effect on the steering voltage, and this allows the frequency to drift just as much as it does with shorter time constants, only at a lower frequency.
None of this would really matter if I had a more stable VFO to begin with as the correction pulses would be applied very infrequently except perhaps during initial warmup, or when the circuit experienced a rapid change in temperature. However, I was hoping to be able to stabilize a more modest VFO with this type of circuit but it is no longer clear to me that I will be able to do so.
I suspect that the answers lie in control system theory and that I should do some more reading on this subject in order to figure out what to try next. I do know that in conventional control systems, up to three inputs are used (P for displacement, I for the integral of displacement, and D for the derivative of displacement is the usual terminology). In this case I'm using only the integral (I), which probably means there will always be some oscillation. Perhaps by adding the equivalent of one or more of the other inputs, I could achieve better results. The problem is I don't think it's possible in this case to add a P or D feedback value. In the first case, there is no fixed voltage that corresponds to a particular frequency, and in order to calculate a displacement value an ADC would need to be added in order to measure the control voltage and to use this to calculate the relative displacement (P) based on previous readings. That is a job for a microcontroller, not a CPLD. And in order to calculate the derivative, I would need to keep at least one past value of P which means that I must calculate P in order to take this to the next step.
I'm going to ponder this a bit more and then decide whether or not to go ahead with this second feedback component to the loop filter. It definitely complicates the circuit to the point where it is more complex than a PLL, and at least as complicated as DDS. Does a well-built LC oscillator really beat out a PLL system which uses a DDS as a reference clock in order to achieve near continuous frequency tuning in terms of phase noise? If not, then I'm not sure it makes sense for me to continue beyond stabilizing my existing VFO and then adjusting the circuit to work with that. I guess I'm starting to see the appeal of those SI-570 chips now!
6837 2011-11-17 07:14:57 Alex P Re: Update on FLL Experiment Neil,
Thankyou for the picture and info on this.
6854 2011-11-19 22:33:47 victor Re: Update on FLL Experiment Try adding a resistor in series with the integrator capacitor (use the larger integrator cap[acitor). Use a trimmer and start from 0 Ohm, increasing slowly its value until it start to affect the oscillati 6855 2011-11-21 05:51:56 Bill Noyce Re: Update on FLL Experiment The 2010 ARRL Handbook (and probably other editions too) has a nice section
on designing filters for PLL's. As Victor suggests, damping the overshoot
can be as simple as adding a resistor. You can use SPICE to simulate your
filter and get the nice amplitude & phase plots (Bode plots) similar to
what's shown in the Handbook article.
-- Bill, AB1AV
> I suspect that the answers lie in control system theory and that I should[Non-text portions of this message have been removed]
> do some more reading on this subject in order to figure out what to try
> next. I do know that in conventional control systems, up to three inputs
> are used (P for displacement, I for the integral of displacement, and D for
> the derivative of displacement is the usual terminology). In this case I'm
> using only the integral (I), which probably means there will always be some
> oscillation. Perhaps by adding the equivalent of one or more of the other
> inputs, I could achieve better results. The problem is I don't think it's
> possible in this case to add a P or D feedback value. In the first case,
> there is no fixed voltage that corresponds to a particular frequency, and
> in order to calculate a displacement value an ADC would need to be added in
> order to measure the control voltage and to use this to calculate the
> relative displacement (P) based on previous readings. That is a job for a
> microcontroller, not a CPLD. And in order to calculate the derivative, I
> would need to keep at least one past value of P which means that I must
> calculate P in order to take this to the next step.
6856 2011-11-21 15:38:59 jasonb1963 Re: Update on FLL Experiment Hi Bill,
Thank you for your comments. I have Floyd Gardner's book on PLLs which I've used in the past when building PLL synthesizers. However, what I've found experimentally is that if I design the type of low pass filter one would use with a PLL and connect it into the FLL circuit that the error pulses from the CPLD create objectionable modulation in the audio spectrum. If I dial down the amplitude to the point that the modulation is no longer audible, then the output of the loop filter is unable to change the frequency sufficiently to compensate for drift. One problem I'm working with is that the error pulses are only produced at the rate of 10 Hz, which is much much lower than most PLL systems I'm familiar with.
Given the extra 90 degrees of phase margin with this type of loop, I thought I would try an integrator for a loop filter. In control systems other than PLLs, this approach is widely used. With very large time constants, this produced the best results I've managed so far with the carrier frequency slowly oscillating a bit above and below the hold value.
The leakage (lag-lead) resistor that Victor suggested earlier was already present in my integrator since the op-amp needs a DC path to ground and will tend to drift due to offset bias unless compensated somehow. However, I did not think to experiment with the values of this resistor until Victor suggested it. Preliminary results are encouraging, but I'm running into another issue which is causing me some grief right now.
My VFO drifts downward in frequency a few Hertz per second. Adding N750 capacitors to the tank circuit only makes it worse so I probably need to put a poly cap in there (positive temp coefficient) only I don't have any that small. If a trimmer has a positive temp coefficient, that might work and I will try it soon.
Anyway, because the VFO drifts downward slowly in frequency, the amount of bias which is necessary to push the frequency back up is quite a bit larger than the amount which is necessary to push the frequency down. My circuit is symmetric so when the frequency drifts a few Hertz above the target frequency, it is pushed down much harder than it should be, and it then takes some time for the loop to bring the frequency back up to the target range. Obviously I'm not working with a high quality VFO here with very low drift, but I was hoping that wasn't going to be necessary with this type of circuit.
So, if I cannot get the VFO to be relatively unbiased in terms of drift, I am going to have to modify the CPLD program so that there are separate outputs for going up and down in frequency and then bias them with appropriately-valued resistors in order to compensate for the drift in my VFO.
Once this is done I think I will be able to make more meaningful measurements regarding the behavior of the loop as it attempts to hold a set frequency and I will resume playing with the leakage resistor on the integrator.
Error signal: 3.75 volts/second initially (+/- 0.375 volts ten times per second), doubling when frequency difference reaches 40 Hertz from target value. If frequency is off by 1 Hz, then an error signal will be asserted once per second.
Integrator RC: Values in the 100-1000 range produce least objectionable modulati
6857 2011-11-21 22:07:18 victor Re: Update on FLL Experiment Jason, it seems to me that inputing a low current into the integrator can compensate the VFO drift, so you don't have to mess with exotic compensating capacitors. just use a resistor trimmer between the integrator power supplies (I hope they are regulated) and a large value resistor (1M? 10M?) between the center pin of the trimmer to the integrator input. Adjust for nulling the drift. I think this will solve the problem of the assimetric operation of the FLL correction.
Victor - 4Z4ME
6861 2011-11-22 20:37:48 jasonb1963 Re: Update on FLL Experiment Hi Victor et al,
I tried a number of variations on the circuit this evening including:
1) Using a trimpot to trim the ground reference voltage for the integrator.
2) Outputting two signals from the CPLD, one for pushing the frequency up and the other for pushing the frequency down. Adding a trimpot to these two outputs in order to vary their relative contributions to the integrator.
3) Adjustments to the loop gain each time a change was made.
4) Varying the leakage (lag-lead) resistor across the integrator capacitor.
In the end, my best results were achieved with (2). The results obtained using a simple 40M VFO with ordinary components which was drifting at about 10 Hz/second without the FLL running were +/- 2Hz over several minutes of monitoring using a frequency counter with 1Hz resolution. Later, I walked away from the FLL while it was running and came back in a half hour and it was still locked, but I have not tried varying the temperature by more than 10-15 degrees so far. There is at least +/- 20KHz of tuning range on the varactor diode to which the output of the loop filter is connected so I expect it can hold the lock over at least 30-50 degrees F without further modifications.
Some further thoughts:
- Better results can almost surely be obtained with a more stable VFO and by building the entire circuit with ugly bug construction rather than using solderless breadboard for some parts of the circuit as I did.
- The FLL cannot correct any rapid deviations caused by physically disturbing it or placing it in close proximity to objects which affect the tank circuit resonance.
- The relatively slow rate at which the error signal is generated (10 Hz in the case of my circuit) dictates very large RC time constants to be used in the integrator loop filter. My best results were obtained with values of 100 or more.
- The high impedances in the loop filter make it vulnerable to stray coupling which means it needs to be well shielded like the VFO.
- It would be nice to dynamically adjust the loop gain based on a function of deviati