EMRFD Message Archive 6812
Message Date From Subject 6812 2011-11-09 19:16:40 jasonb1963 Frequency Locked Loop
Here is what I did and some initial results from testing:
I wrote some code for the CPLD I used earlier to build a simple frequency counter with. I hooked up a 4MHz crystal oscillator to the CPLD and wrote one process to divide it down to a 10Hz clock which I used for gating (using a 19-bit signed register to do the division).
Now with gate signal in hand, I count the frequency with a 12-bit signed integer. It overflows, of course, but that's not a problem for what I'm doing. The lock range is approximately 10Hz (gate clock) * 2^12 = 40.96KHz = +/1 20.48KHz -- plenty for most VFO purposes, and far better than you get with a 1-bit huff-n-puff circuit.
When the user presses the lock button, another process begins to function. When the button is pressed, the current contents of the count (at the end of the gate clock) are written into another register. Now on each gate clock, the current count is compared to the stored count and depending on whether it is smaller or larger, an output it set or reset.
I feed this output bit into a leaky op-amp integrator circuit. The 90 degrees of phase lag should not be an issue because we have 180 degrees to start with as opposed to the 90 degrees you have in a PLL circuit.
So what I did this evening was hook up a HP 3325A signal generator to the input of the CPLD. I connected up the output of the op amp to my voltmeter, and had a "low" and "high" LED connected to the signals on the CPLD that indicate whether the frequency is high or low.
After a bit of debugging, everything worked. Actually better than expected. As soon as I pushed the "lock" button, I could watch the output of the op amp track the input frequency very precisely. If I went 1Hz up, the op amp would reach one rail in a few seconds. If I went 1Hz down (from the initial frequency), the op amp would reach the other rail in a few seconds. This suggests that the system will hold a VFO to +/- 1Hz with a 10Hz gate. Actually I'm not sure the gate time has a lot to do with how accurate it is since the integrator measures the average of each cycle's output anyway.
The only thing I haven't done yet is connect the circuit to an actual VFO. I started building a test VFO to try it out on (7MHz) and hope to have some more results tomorrow. If that works as expected, I will move forward with a 15M VFO.
For anyone that's interested in combining this with a frequency counter, I believe you will need the next larger CPLD chip -- the XC95144 because I don't think it's possible to fit both in the limited amount of logic present on this chip.
I see the next step beyond merely locking a user-tuned frequency would be to allow the user to directly specify a frequency within the range of the VFO. This should be possible by using more than one output bit to change the frequency -- higher order bits for coarse adjustment and low order bits for fine adjustment. All easily done with a simple subtraction operation on the CPLD. And if I'm not mistaken, this approach offers a number of advantages over the traditional PLL circuit:
Let me preface what I say next by saying that I am by no means an expert on this subject so it is possible (likely even) that I may have gotten something wrong. This is based on my best understanding from what I have learned by reading about, designing, and building PLL circuits in the past:
First, you are not limited to a tuning frequency which is an integer multiple of your reference frequency. This is a big win because the reference frequency of a PLL needs to be well above your modulation bandwidth because it is present in the phase detector output and needs to be filtered out before the signal reaches the VCO. You aren't going to get any fine tuning out of a PLL without some additional tricks.
Second, there is no phase detector and associated noise which gets into your VCO and degrades the phase noise. Instead, you are using a very low frequency output (gate clock frequency) to drive an integrator which controls the VCO. Any noise that gets into the VCO from this will be much lower in frequency to that from a phase detector and should have a much smaller effect on the phase noise performance of the VCO.
Third, you have more phase margin to work with because there is no phase to frequency conversion in the loop.
I haven't seen this approach mentioned in any of the amateur literature that I've read, though I would be extremely surprised if others have not already exhaustively explored the subject. Still, it seems like it should offer good performance for very modest complexity for the amateur hobbyist.
--
Jason6813 2011-11-09 22:50:43 Ashhar Farhan Re: Frequency Locked Loop
This is just amazing. Hans summers is our resident HnP expert. Hans, do u copy?
More on this later...
- farhan VU2ESE
On 11/10/11, jasonb1963 <jasonb1963@yahoo.com> wrote:
> Related to my ongoing effort at making a 15M transceiver without using a
> SI-570 or DDS chip, I thought I would try a frequency locked loop to
> stabilize an LC oscillator. The idea occurred to me during the discussion
> of the CPLD-based frequency counter and someone mentioned that it might work
> well for huff-n-puff frequency control. Taking that a step further, you get
> a frequency locked loop.
>
> Here is what I did and some initial results from testing:
>
> I wrote some code for the CPLD I used earlier to build a simple frequency
> counter with. I hooked up a 4MHz crystal oscillator to the CPLD and wrote
> one process to divide it down to a 10Hz clock which I used for gating (using
> a 19-bit signed register to do the division).
>
> Now with gate signal in hand, I count the frequency with a 12-bit signed
> integer. It overflows, of course, but that's not a problem for what I'm
> doing. The lock range is approximately 10Hz (gate clock) * 2^12 = 40.96KHz
> = +/1 20.48KHz -- plenty for most VFO purposes, and far better than you get
> with a 1-bit huff-n-puff circuit.
>
> When the user presses the lock button, another process begins to function.
> When the button is pressed, the current contents of the count (at the end of
> the gate clock) are written into another register. Now on each gate clock,
> the current count is compared to the stored count and depending on whether
> it is smaller or larger, an output it set or reset.
>
> I feed this output bit into a leaky op-amp integrator circuit. The 90
> degrees of phase lag should not be an issue because we have 180 degrees to
> start with as opposed to the 90 degrees you have in a PLL circuit.
>
> So what I did this evening was hook up a HP 3325A signal generator to the
> input of the CPLD. I connected up the output of the op amp to my voltmeter,
> and had a "low" and "high" LED connected to the signals on the CPLD that
> indicate whether the frequency is high or low.
>
> After a bit of debugging, everything worked. Actually better than expected.
> As soon as I pushed the "lock" button, I could watch the output of the op
> amp track the input frequency very precisely. If I went 1Hz up, the op amp
> would reach one rail in a few seconds. If I went 1Hz down (from the initial
> frequency), the op amp would reach the other rail in a few seconds. This
> suggests that the system will hold a VFO to +/- 1Hz with a 10Hz gate.
> Actually I'm not sure the gate time has a lot to do with how accurate it is
> since the integrator measures the average of each cycle's output anyway.
>
> The only thing I haven't done yet is connect the circuit to an actual VFO.
> I started building a test VFO to try it out on (7MHz) and hope to have some
> more results tomorrow. If that works as expected, I will move forward with
> a 15M VFO.
>
> For anyone that's interested in combining this with a frequency counter, I
> believe you will need the next larger CPLD chip -- the XC95144 because I
> don't think it's possible to fit both in the limited amount of logic present
> on this chip.
>
> I see the next step beyond merely locking a user-tuned frequency would be to
> allow the user to directly specify a frequency within the range of the VFO.
> This should be possible by using more than one output bit to change the
> frequency -- higher order bits for coarse adjustment and low order bits for
> fine adjustment. All easily done with a simple subtraction operation on the
> CPLD. And if I'm not mistaken, this approach offers a number of advantages
> over the traditional PLL circuit:
>
> Let me preface what I say next by saying that I am by no means an expert on
> this subject so it is possible (likely even) that I may have gotten
> something wrong. This is based on my best understanding from what I have
> learned by reading about, designing, and building PLL circuits in the past:
>
> First, you are not limited to a tuning frequency which is an integer
> multiple of your reference frequency. This is a big win because the
> reference frequency of a PLL needs to be well above your modulation
> bandwidth because it is present in the phase detector output and needs to be
> filtered out before the signal reaches the VCO. You aren't going to get any
> fine tuning out of a PLL without some additional tricks.
>
> Second, there is no phase detector and associated noise which gets into your
> VCO and degrades the phase noise. Instead, you are using a very low
> frequency output (gate clock frequency) to drive an integrator which
> controls the VCO. Any noise that gets into the VCO from this will be much
> lower in frequency to that from a phase detector and should have a much
> smaller effect on the phase noise performance of the VCO.
>
> Third, you have more phase margin to work with because there is no phase to
> frequency conversion in the loop.
>
> I haven't seen this approach mentioned in any of the amateur literature that
> I've read, though I would be extremely surprised if others have not already
> exhaustively explored the subject. Still, it seems like it should offer
> good performance for very modest complexity for the amateur hobbyist.
>
> --
> Jason
>
>
>
--
Sent from my mobile device6814 2011-11-10 06:38:26 Alex P Re: Frequency Locked Loop
Alex