EMRFD Message Archive 2419

2419 2008-11-18 14:42:40 ha5rxz PLL Will Not Lock Message Date From Subject I am experimenting with a basic phased locked loop based on the circuits shown in EMRFD, my problem is that the PLL will not lock. I am using a 45 MHz VCO which is divided by nine and then compared at the phase detector with a 5 MHz reference. The 5 MHz and 45 MHz oscillators are providing the right levels and the divider is working. The only thing I am not sure of is what happens if a phase detector has a signal on one of the inputs which does not have a 50/50 mark space ratio. The output from the divide by nine is low for eight input cycles and high for one. Is this my problem and (if so) how do I divide an oscillator by nine and get a 50/50 output? HA5RXZ ----- Original Message ----- the easy way to get a square waveform is to divide both your fequencies by two using a d flip flop. keep your ref frequency at 2.5mhz instead of 5. the other way is to pass them both through half-wave filters. - f On 11/18/08, ha5rxz wrote: > I am experimenting with a basic phased locked loop based on the > circuits shown in EMRFD, my problem is that the PLL will not lock. I > am using a 45 MHz VCO which is divided by nine and then compared at > the phase detector with a 5 MHz reference. > > The 5 MHz and 45 MHz oscillators are providing the right levels and > the divider is working. The only thing I am not sure of is what > happens if a phase detector has a signal on one of the inputs which > does not have a 50/50 mark space ratio. The output from the divide by > nine is low for eight input cycles and high for one. > > Is this my problem and (if so) how do I divide an oscillator by nine > and get a 50/50 output? > > HA5RXZ > > Thank you for all of the replies. The circuit I am using for a phase detector appears on page 4.20 of EMRFD and is marked Figure 4.39. There is an SBL-1 used as the phase detector with an LM358 based filter following this. The reference signal and the divided VCO can be applied to either input as the inputs are interchangable. The output of the LM358 shows a DC signal at about 6v which is modulated by what appears to be random rubbish. By removing the output of the divider and feeding the second input with the output of my signal generator the output of the phase detector is clean so I think this is a divider problem. There are lots of patents relating to odd number dividers but not much clear information. I'm not a digital engineer so I need to go slowly with this part. I can read data sheets and follow schematics but that's just about it. The idea of using a 2.5 MHz reference and dividing by eighteen is an interesting one but I don't have a 2.5 MHz crystal handy. HA5RXZ Hi Peter, et al, Well, I suspect that the problems you have found with the PLL have to do with the diode ring phase detector that you are using. This is very much a phase detector, and not phase-frequency. It wants to see signals over the whole operating cycle of both inputs. So, I would run your present signals through low pass filters to get rid of most of the sharp edges. You may then have to amplify the results to get them up closer to the +7 dBm level that I used in the experiment presented in the book. That particular experiment used N=1. That is, it was just a 1