EMRFD Message Archive 14865

Message Date From Subject
14865 2018-06-03 10:46:05 Andrea Baldoni CD JFET Hartley - resistor question
Hello All.

This is the first my post, thanks to all for the nice group I follow since

I built a very simple common drain JFET hartley oscillator, about 500kHz, and I
am observing a behaviour I would like to understand better.

I can post a picture of the circuit if it's allowed, however I think a
description is enough, the components are just few.

Drain is at a bypassed +5V.
Tank is a parallel C+L, one side of L grounded, the other side to gate.
L has a tap, it go to source through a 1k resistor bypassed with 100nF that
serve to reduce JFET current to about 4mA.

Oscillator works. Position of the tap is such that gate diode don't reach
conduction, waveform is pretty sinusoidal, etc...

Now the question.

L is wound on a ferrite core toroid so I thought not to let DC pass in it.
It's not a problem anyway, the current is minimal, but why not to experiment?

So I moved the 1k resistor that was between source to the tap of L, from source
to GND. The capacitor still go from source to the tap of L.

The circuit should be completely identical on the 500kHz AC profile:
DC now goes to GND (but it went to GND even before, through the absolutely
negligible resistance of L). AC goes to L, through the 100nF capacitor
that has 3 ohm Z.

Oscillator stopped to work, I had to increase feedback (much) to restore
oscillation. With the same feedback, the previous configuration give much
higher output levels anyway.

Things I already thought:

- before, C represented a high pass filter with a rolloff on low frequencies,
now there's not any rolloff and it's a pure integrator, but it shouldn't matter
as the cutoff was at 10kHz and oscillator is at 500kHz

- the DC on the ferrite doesn't change anything. I injected 4mA on the coil
from another supply and the situation didn't change

- letting the 1k in the new position and adding another 1k through the 100nF
capacitor, restore the higher output levels. It also change the JFET current
of course, but it seems that's not the point

- bypassing the C lowers it's Q, but we are speaking of a Z of 3 ohm vs. a
resistor of 1k

Thank you!

Andrea Baldoni
14866 2018-06-03 11:08:51 Bill Carver Re: CD JFET Hartley - resistor question
In your original connection of the 1K resistor the impedance seen by the tap is the 0.1 uF capacitor in series with the resistance of the source. Which is almost totally just the resistance of the source. A first-approximation if the source impedance is 1/Gm: I don't know your JFET, so can't look at Gm v.s. Id to get a number for the Gm. But you can look at a data sheet for Gm v.s. Id, and calculatea number for the source load resistance on the tap.

By moving the resistor, you how have added 1K resistance to the load to the tap. And the 1/Gm of the JFET is still there, too, so the total load is 1/Gm and 1K in parallel.  I would guess this additional load reduces the feedback enough to stop the oscillation. As a test, move the 1K resistor back to its original position. Oscillating, yes? OK, now take another 1K resistor and place it from tap to ground. If oscillation stops, that confirms my guess moving the 1K and adding it to the tap load was correct.

No problem with the idea of experiment, but It is very, very, very unlikely that 4 mA of current through the bottom winding on the core will cause any problem of saturation or hysteresis for the ferrite. However, if you wish to see the effect of that DC, you can do it: just connect the 1K source bias resistor in series with a large inductance to ground, so it can pass the 4 mA through that choke instead of through your toroid. But very little RF can flow through the 1K because of high choke impedance. To have virtually no effect, make the choke at least 10K ohms at 500 KHz. That would be 3 millihenries. 3 mHy is not an extremely common value, maybe you have a 10 mHy RF-style choke. Measure the DC resistance of the choke: it should be small compared to 1K so its DC resistance to not alter the bias point of your FET and change the experiment!

With the choke in place no DC is going through the toroid like you want to see, and the 1K resistor load is not seen by the tap because of the choke. The tape now sees just the JFET source impedance. If this thinking is correct, it should be oscillating again.

Bill  W7AAZ

14867 2018-06-03 21:39:01 victorkoren Re: CD JFET Hartley - resistor question
Your last sentence touched the important point. In your first configuration the resonant circuit was the inductor and the resonator capacitor. This certainly has a high Q. You adjusted the L tap to just get oscillations so the 1/Gm output resistance of the Jfet source lowered the Q just slightly.
In the second configuration the bypass capacitor with the parallel resistor are inside the resonator. Even if the Xc is just 3 Ohm, having the 1K resistor in parallel with it and maybe having capacitor with high ESR (effective series resistance) might lower the resonator Q in a way that stops oscillation.
What is the capacitor type? 100nF ceramic capacitors might be a capacitor with high ESR. Try substituting it with a larger value poly-mylar etc. capacitor which might have lower ESR at those low frequencies and check again.
Victor Koren - 4Z4ME
14868 2018-06-04 09:36:03 Andrea Baldoni Re: CD JFET Hartley - resistor question
14869 2018-06-04 09:37:07 Andrea Baldoni Re: CD JFET Hartley - resistor question
14870 2018-06-04 10:23:06 Rob Re: CD JFET Hartley - resistor question NO SCHEMATIC
I do not see a schematic.
There is one sentence at the end of the email that says:
[Non-text portions of this message have been removed]

Please email the schematic to me and I will post it on my web page to share with everyone else....
send to  roomberg@ptd.net

14871 2018-06-04 11:20:19 Rob Re: CD JFET Hartley - resistor question THIS SCHEMATIC
14872 2018-06-04 13:09:17 Bill Carver Re: CD JFET Hartley - resistor question
OK......I actually thought Gm at 4 mA was going to be lower than that, but I look at the data sheet and you're right, it is about 10,000. So the JFET alone loads the tap with out 100 ohms.
It is a little surprising just another 1000 ohms would cause oscillation to stop, but it's not impossible that the oscillator is close to that limit.

Suggestion: with either A or C, put a larger resistor from the tap to ground. Say 10K. In parallel with the estimated 100 ohms of the JFET, that would only decrease the FET current in the tank by 1% and it would be surprising to have 10K stop oscillation. How about smaller....how low can you go before oscillation stops?

Coils wound on ferrite cores come close to analysis as if there is perfect coupling between all the turns of the coil. So the impedance ratio between tap and top of the coil would be the turns ratio squared, times the load on the tap of approximately 100 ohms. I don't remember your turns, but if you had 30 turns total and tap at 5 turns then the JFET would appear as about 36 x 100 ohms, or 3.6K. An interesting calculation, perhaps useful if you want to compute the "Q" of the resonant LC circuit.

14873 2018-06-04 13:44:25 Dana Myers Re: CD JFET Hartley - resistor question
14875 2018-06-05 08:53:40 Andrea Baldoni Re: CD JFET Hartley - resistor question
14876 2018-06-05 10:22:51 Bill Carver Re: CD JFET Hartley - resistor question
Aha.............one end of the toroid is grounded, yes? If total turns is 12, the tap should be closest to that grounded end (with the tap 2 turns up from the bottom, that is normally described as "tap at 2 turns").
Bill - W7AAZ

14878 2018-06-06 12:07:35 Andrea Baldoni Re: CD JFET Hartley - resistor question
14879 2018-06-06 12:58:42 w7zoi Re: CD JFET Hartley - resistor question
Hi Andrea,

Congratulations for actually building and measuring some circuits.   Let me comment on your postings regarding oscillators:

The tap on the Hartley oscillators is usually near the ground end.   That way, any loading from either a bias resistor or the input impedance of the JFET source-gate port does not severely load the oscillator tank.   Your topology will compromised the tank Q.

You said that you used a ferrite core, but never, as I recall, told us the ferrite material.    It makes a big difference.   Your operating frequency was about 500 kHz, again from my memory of prior posts.   At that frequency, you could get quite high Q with a -61 Amidon ferrite.   I've measured values as high as 400 to 500.   But if you tried to use an Amidon -43 material, the unloaded Q would be down at 10 or so.   Oscillation is still possible, but it is going to be a useless oscillator with terrible phase noise as well as a lot of drift.

You mentioned "saturation" in the transistor.    This does not happen in the usual oscillator.   The mechanism that controls the amplitude is current limiting.    In your case, you have a source bias resistor.   This will limit the average current to the current that flows when oscillation is stopped.   (You can stop oscillation merely by temporarily soldering a wire across the tank inductor.)   I think you said current was 4 mA.  Anyway, as oscillation builds up when the circuit is turned on, you will get rectification of the building signal on the gate.   This will lead to an average DC level on the gate that drives the average gate voltage negative toward pinchoff.    The result is current limiting.     If you were to use a gate diode, that diode would rectify the high RF voltage on the tank to create a negative voltage that drives the FET toward pinchoff.   The limiting is described in detail in the early parts of Chapter 4 of EMRFD.    If the diode scheme is used, the bias resistor can be eliminated.

These things can be measured if you have a dual channel oscilloscope with a couple of 10X probes.   It is really interesting to build a JFET Hartley without a diode gate detector and without a source bias resistor.    This then is nothing more than an exact replacement for a classic vacuum tube oscillator.     The circuit will oscillate, but stability and noise are both bad.   I first observed this in 1969 (the first time I had a real oscilloscope, a Tek 647, in my home lab) with one 10X probe on the FET gate and the other on the FET source.  Both traces were on screen.  At one part of the cycle, the FET gate and the source were both up at the drain voltage, the power supply.    The FET was no more than a low valued resistor across the tank.   This limited the level, but also killed the Q.   I had seen an earlier QST article (Hanchett, Dec 1966) where a diode had been used to provide "gate leak" bias in a MOSFET oscillator.    I tried the same thing with the JFET and it immediately solved the problems.    The gate voltage never went above 0.6 volt.   The peak source voltage was higher, but it never got up to the drain voltage.     The stability immediately improved, as did the noise.    These results were presented in a Dec 1970 QST paper.

The JFET is preferred over a MOSFET in this circuit.   The long term stability is the same, but the MOSFET has much higher low frequency noise than a JFET.    Low frequency (1/F) noise is a bad thing in any active device to be used in an oscillator circuit.  The high signal levels in the oscillator and the non-linear device characteristics serve to mix the noise with the carrier, creating noise sidebands.   This is mostly phase noise.   It was many years later when I did experiments to observe the same problem with GaAsFETs, which also make poor oscillators.

Take a look at the regen receiver in EMRFD Fig 1.13.   The detector circuit is again just a JFET Hartley, here with a source resistor for bias.   However, there is no tapped inductor.   Instead, two inductors (L1 and L2) were used, each on toroids.  There is virtually no magnetic coupling from one inductor to the other.   The oscillator performance is still the same.    The tank is now two inductors and one capacitor.   This variation of the Hartley is the exact dual of a Colpitts that uses two capacitors and one inductor.     

Bill Carver (W7AAZ) mentioned the FET impedance of about 100 Ohms that loads the tank.    Yes and no.   This is indeed the situation when the oscillator is starting.    That is, it is the condition when power is first applied, but oscillation has yet to begin.   But as the noise that is in the circuit elements is applied to the FET and is amplified, oscillation builds and limiting occurs.    With limiting comes a change in the FET input impedance.   Impedance may be low during part of the cycle, but will be higher over other parts.    The loading from the FET will not be as bad as you would have with the 100 Ohms that Bill mentioned.    Impedance is generally a small signal steady state concept, conditions that disappear in an oscillator.

I described some measurements above.   These can really be a lot of fun and very instructive.   Most of us have the dual trace 'scope that is required.   You can also simulate these effects with computer SPICE modeling.    LT SPICE does a wonderful job with many of these things, although it does not do any large signal noise simulation.     If you do try the computer simulation, I urge you to also do the measurements.     Then compare the simulations to the measurements.   

Anyway Andrea, keep experimenting and thinking about oscillators. They can be great fun.
Good luck.

73, Wes

14880 2018-06-06 14:12:59 Dana Myers Re: CD JFET Hartley - resistor question
14881 2018-06-06 14:41:11 Bill Carver Re: CD JFET Hartley - resistor question
Of course you're right Wes: the approx 100 ohm source impedance applies before oscillation starts, and is the case if it's won't oscillate at all.  But once running most oscillators are not "small signal".

Andrea mentioned the gate was connected to the top of the tank. I saw no mention of a coupling capacitor, resistor or a diode but if it won't oscillate, the absence or presence of those things wasn't a factor so didn't even touch that issue. Now that it IS oscillating, let the optimization begin!

Bill  W7AAZ

14882 2018-06-06 14:50:33 Bill Carver Re: CD JFET Hartley - resistor question
Well it's oscillating, and if its performance is what you expect/want OK. However that's not the usual configuration. As you're using it, the tank is heavily loaded by the JFET with the source that close to the top of the tank. That drastically reduces the Q of the tank, and the frequency is LESS controlled by the tank and MORE affected by external impedances.

Wes has a book "Introduction to Radio Frequency Design" that discusses factors that control/limit the amplitude of oscillation. I heartily recommend it, at library perhaps. For that topic, and many, may others, that book provides a lot of "insight" into what's going on, as well as the applicable mathematics......which by itself sometimes doesn't provide the same insights.

Bill   W7AAZ

14883 2018-06-06 18:37:54 Eric J Re: CD JFET Hartley - resistor question

If you replace the standard.jft library in LTSpice with the replacement standard.jft library available at the LTSpice Wiki, you can call up the included J310 (and hundreds more jfets) like any library component with a simple right-click.


You can also replace the standard.bjt, *.dio, and *.mos libraries and have virtually every component of this type mentioned in EMRFD and common in the QRP and experimenter community.

No downside other than larger library files. Most standard.* files that come with the current LTSpiceXVII are around 35K. The replacements are around 350K. If that's a problem, you can just extract what you need.

Eric KE6US