EMRFD Message Archive 14086

Message Date From Subject
14086 2017-06-28 00:16:23 Hans Summers Si5351A: facts and myths

Hi all

Forgive the long post please. I have extensive experience of the Si5351A now as many of the QRP Labs products are based around this miraculous little chip. So to some extent, I do know something about what I am talking about here ;-)


This confuses a lot of people so just to clear this up at the start. DDS is Direct Digital Synthesis which simulates a sinewave by accumulating numbers in an internal register at regular intervals (determined by the system reference oscillator e.g. often 125MHz for the simple AD9850 DDS modules that are common). This accumulated count goes to a Digital To Analogue converter (DAC) in the chip, and through an anti-aliasing filter (which you must add external to the chip). Due to the discrete stepped nature of the simulated output sinewave, the frequency spectrum has spurs and this is a feature of DDS. Higher ratio of reference to output frequency, and wider DAC bit width both reduce the spurs. Analog Devices has market dominance of DDS chips and some very expensive high end chips as well as the more common cheaper ones. 

The SiLabs Si5351A and Si570 chips implement a totally different Phase Locked Loop (PLL) based method of synthesising arbitrary frequencies. The Digital PLL is all inside the tiny 3 x 3mm chip and replaces an entire circuit board of earlier synthesisers some decades back! The chip multiplies a 27MHz (or 25MHz) reference up to an internal Voltage Controlled Oscillator (VCO) in the range 600-900MHz, which you can then divide down to get the desired output frequency. Any PLL has the characteristic of adding phase noise to the crystal reference frequency. How much phase noise is added depends on many factors, particularly the loop bandwidth - in the Si5351A and Si570 the loop bandwidth is low (slow loop) and this really makes the phase noise very low. 

I just mention this because a lot of people seem to mistakenly refer to the Si5351A as a "DDS" which it totally is not! And also to be clear that a feature of DDSs is spurious outputs (like birdies in a receiver) whereas a feature of PLLs is phase noise. Nothing is for free! In modern devices I think that for the majority of applications both of these undesirable features are usually negligible.

Upper frequency limit: 

The upper frequency limit of the Si5351A-B chip is 200MHz. Not the widely circulated 160MHz. The 160MHz applied to the earlier chip revision. The QRP Labs Synth kit http://qrp-labs.com/synth uses the current -B revision (200MHz limit) and I expect any other hobby boards using this chip are also using the -B revision of the chip. 

Practical frequency limits: 

The practical frequency limits are even wider than the datasheet suggests. The datasheet says the internal VCO frequency should be 600-900MHz. If you are prepared to disrepect this specification, then who knows what performance parameters may be affected, but it DOES at least seem to work... bear in mind that in any case, some performance parameters degrade with frequency in any case, so your own frequency limit might be lower. The configuration registers of the Si5351A can be configured to allow operation down to 3.5kHz. The upper limit, determined here by measurement, was approx 292MHz. Other QRP Labs kit builders have also confirmed similar figures. Beyond 292MHz my Si5351A simply stopped producing an output. The cut-off was quite sudden. 

Phase noise compared to Si570: 

Perhaps one of the biggest (probable) myths, is that the Si5351A has high phase noise so we shouldn't use it if we care about noise! Of course every application does have different requirements and trade-offs are always present. Base the trade-offs on reality though not on rumour. The Si5351A and Si570 might be said to come from the same family of digital PLL chips but they do have a lot of differences. 

The Si5351A multiplies the 27MHz (or 25MHz) crystal reference up to an internal PLL frequency of 600-900MHz. Then it is divided down in the so-called "Multi-synth" stages to produce the desired output frequency (or frequencies). Both the multiplication up, and the division down, are fractional divisors - an integer and a fractional part made of 20-bit numerator and denominator. 

The Si570 has an integer-only division ratio down to the output frequency. The Si5351A has a fractional division ratio. The Si5351A datasheet recommends using even integer divisors to minimise output jitter (a.k.a. phase noise). This makes sense! Think about dividing by 2 a few times, it is a relatively clean process. On the other hand if you divide by 45 and 132,448 / 382,124ths for example, you can imagine that the fractional division will result in a messy output pulse stream. In other words, much worse phase noise. 

The jitter specifications in the Si5351A datasheet are noted to be "worst case, real world" and it says they "Jitter is highly dependent on device frequency configuration". We don't know what configuration they used and whether they used even integer or not. The "worst case" note seems to imply not. SiLabs documentation is quite poor in some respects. 

I'm saying you can't just compare datasheet jitter specifications... a lot of evaluation and measurement would probably be needed side by side to determine how the Si5351A really compares to the Si570 in actual use. 

All the QRP Labs firmware (and example source code) use the minimum jitter even integer divider mode. 

Note also that Elecraft use the Si5351A in the KX2, not the Si570. Everyone knows Elecraft make great radios. So there's a fair argument that what's good enough in an Elecraft rig cannot be too bad ;-)

Both an Si5351A and an Si570 would be worse phase noise than a crystal... but then again, a crystal isn't movable over 3.5kHz to 292MHz... An interesting article on the QRP Labs website by Gwyn G3ZIL about comparing the Si5351A to a crystal LO in a practical receiver. The article is interesting not just because of its conclusion that an Si5351A does a great job for practical real world purposes, but also because it stresses the importance of clean supplies when using the Si5351A. Noise on the supply line does easily modulate the Si5351A output. So keep that in mind when designing around the Si5351A. See http://www.qrp-labs.com/synth/synthnoise.html

The controversial PLL reset and audio "pops":

Yes, when you do a PLL reset, it interrupts the output frequencies for some milliseconds and that will make a nasty "pop" in your audio. This PLL reset is one of the most misunderstood aspects of using the Si5351A. For good reason! The SiLabs documentation is poor and does not explain clearly when you need it and when you do not! I know that there is the knowledgebase article http://community.silabs.com/ mgrfq63796/attachments/ mgrfq63796/Timing_Discussion% 40tkb/61/1/311668.pdf dealing with the topic, which says a PLL reset is required every time the PLL feedback registers are changed. This document also refers to another KB article 311538 which when you open it, mysteriously contains exactly the same contents as 311668. Which is typical of the Si5351A documentation - even the AN619 (choosing a register map) contains lots of errors and duplication caused by copy-and-paste without subsequent necessary edits. I don't want to be too harsh because I know only too well it is quite a big job, keeping documentation all in order. 

When you first set up the Si5351A registers the first time, you need to do a PLL reset otherwise nothing works. You do NOT need to do a PLL reset for subsequent PLL feedback divider changes! I have not been able to find any size of frequency change where a PLL reset is required. Certainly incrementally tuning across an amateur band requires no PLL reset. Given the datasheet comments and the fact that evidently you do at least need one PLL reset at the start, I remained a bit nervous and in my code I do generate a PLL reset when there is a "large" frequency step... what does "large" mean, who knows. I arbitrarily set it to 10kHz and no QRP Labs customer has ever had a problem with it to the best of my knowledge. 

What the datasheet does NOT tell you, is that if you wish to use the phase offset feature to maintain an accurate and constant phase offset between two of the Si5351A outputs on the same frequency - then you MUST do a PLL reset under two circumstances:

1) Every time you change the MultiSynth divider (whether integer or fractional) - note, the MutliSynth divider! Not the PLL feedback divider! Which is kind of opposite to the documentation... but trust me, this is the way the chip actually works

2) Every time you switch the outputs on/off using the Clock Control registers e.g. Register 16. If you are about phase relationships, INCLUDING if you have simply set a 180-degree phase relationship to another clock output using the clock invert bit in the clock control register, even then, you have to do a PLL Reset.

If you don't do the PLL reset under these two circumstances then the phase offset will be random. Frequency will be fine though - this part of the PLL reset discussion only applies to when you wish to have a precise phase offset between outputs. Examples which I use are when you want push-pull outputs (180-degree phase difference), some people use this for driving a LF PA; or when you want 90-degree phase offset for switching a Quadrature Sampling Detector type mixer which requires a quadrature LO. 

I have not seen any of this anywhere in SiLabs documentation, I reached the above conclusions after hours and hours of experimenting...

It is very interesting to me that the few circumstances in which a PLL reset is actually required, apparently are related to the use of the MutliSynth Divider stage of the chip - not the PLL! It almost makes me wonder if this PLL reset register is totally misnamed and totally misunderstood - should it really be called the "MultiSynth Reset Register"? 


There is a view that programming the Si5351A is difficult - or perhaps, much more difficult than a DDS chip. I would agree that it is more difficult conceptually than loading a 40-bit tuning word into a DDS. But not MUCH more difficult! Sure, you have to get your head around the Si5351A. You had to get your head around the DDS too, it's just that the DDS has been around for longer and we have got more used to it. 

In either case, the internet is now full of examples and libraries of how to use both families of devices, so you can easily use either without much deep understanding of how they work. QRP Labs has example code for AVR, PIC and Arduino http://qrp-labs.com/synth and is just one of many sites publishing source code for the Si5351A.

The above discussions on PLL reset maybe sound scary but remember, the only reason we can discuss all this is because the Si5351A has a much greater capability and feature set in many ways, then a DDS. The multiple outputs for example, which can be on different frequencies or different phase shifts. 

Requirement for TCXO

A TCXO has two benefits - first, as it is a Temperature Controlled Crystal Oscillator, it exhibits very low temperature dependence compared to an unstabilised crystal oscillator. The second benefit is that if you buy a 27MHz TCXO then without any further discussion, when you just power it up, the output frequency will be much closer to 27MHz than a crystal oscillator would be. For example we find that in the QRP Labs synth the 27MHz crystal typically operates at around 27.004MHz +/- 1kHz. So if you want an accurate synthesiser, then you need to measure this value and compensate for it in the Si5351A register configuration (easily done in firmware). 

For all but the most demanding applications, I think the extreme frequency stability is not really necessary; and in many cases measurement (a one-off calibration) is possible so a regular crystal does just fine. Even in very demanding applications like weak signal narrow band modes (e.g. used in the Ultimate3S transmitter http://qrp-labs.com/ultimate3s/u3s ) a basic crystal has been shown to be good enough across HF and even VHF all the way up to 2m. QRP Labs App Note AN001 http://qrp-labs.com/appnotes discusses some techniques to deal with the drift - without a TCXO. 

Bear in mind also that many of the less expensive TCXOs use a digital compensation method, where they measure the temperature digitally then apply a correction to the pull the crystal oscillator. In many cases the result is discrete steps on the output frequency, of several Hz. That can be enough to disrupt any weak signal narrowband work! 

So just weigh all this up before automatically assuming you need a TCXO. The QRP Labs Si5351A Synth kit http://qrp-labs.com/synth has PCB footprints for a TCXO if you wish to use it, but personally I have not found it to be necessary. 


So I hope this helps someone... when I started writing this I was only going to comment on the PLL Reset topic, and on the fact that the current chip revision has a 200MHz specified upper frequency limit. But I ended up adding a lot of other info. 

73 Hans G0UPL

14087 2017-06-28 01:12:09 Tony Fishpool Re: Si5351A: facts and myths
Fantastic article Hans. Thanks for taking the trouble.

Tony G4WIF

Hi all

Forgive the long post please. I have extensive experience of the Si5351A now as many of the QRP Labs products are based around this miraculous little chip. So to some extent, I do know something about what I am talking about here ;-)
14088 2017-06-28 02:11:48 Ravi Miranda Re: Si5351A: facts and myths
Excellent article!! Thanks for explaining this so well!! :-)

14089 2017-06-28 06:43:05 Nick Kennedy Re: Si5351A: facts and myths
That's a keeper!


Nick, WA5BDU

So I hope this helps someone...
14090 2017-06-28 08:23:34 Dale Hammer Re: Si5351A: facts and myths


Great explanation !  Thank you.


Dale  K9NN


14093 2017-06-28 09:06:28 victorkoren Re: Si5351A: facts and myths
Hans, nice article. However the PLLs we use are Fractional-N PLL so by definition they have both Pll phase noise but also spurs. They do have techniques to minimize the spurs amplitude, like noise shaping but they are still there and you might find them at specific problematic frequencies.
Victor - 4Z4ME
14094 2017-06-28 10:06:48 aa0zz Re: Si5351A: facts and myths
Very nice, Hans. Thanks for clearing up a number of questions that I had.  You've spent the long hours in the lab experimenting and have found the answers the hard way so that's greatly appreciated. The Silicon Labs documentation is lacking many important details and has many errors, as you say, so it remains up to us to figure it out.  It's nice that we can then share this knowledge.
Thanks to you and others, there are many Si5351 examples out there now and libraries are becoming available for folks to implement. This doesn't quite satisfy some of us that want to dig deeper into the internals so we can understand and control the various aspects / features / anomalies.  
-Craig, AA0ZZ

14095 2017-06-28 10:08:37 Dana Myers Re: Si5351A: facts and myths
14096 2017-06-28 10:49:15 Dana Myers Re: Si5351A: facts and myths
14097 2017-06-28 11:05:50 rcbuckiii Re: Si5351A: facts and myths

Excellent article and thanks for sharing your knowledge with us. I copied the entire article and pasted it into Word for future reference. I'm guessing you read the responses to my post about the grounded gate amplifier for the receiver I am building and decided to create your post. Based on your article, I am going to use the Si3531 as the LO in my 40/20 receiver.


Thanks for your comments. I also copied your comments and put them into the same Word doc as Hans. I will use the higher VCO and larger output divider numbers you suggested. Those numbers work for 20 meters with a 9 MHz IF. I will use a similar approach for 40 meters.

14098 2017-06-28 18:47:25 bwbangerter Re: Si5351A: facts and myths
First of all Hans, thank you very much for the informative and well-written post regarding the SI5351A.  I recently bought a BITX40 transceiver, and have been using the included Raduino controller to examine some characteristics of the included SI5351A chip.  In particular, I have been trying to understand the output circuitry of the chip.  The data sheet states that the output impedance is 50 ohms, though the measurements I have made with a variety of resistive loads convince me that it is not a 50 ohm source impedance in the conventional sense, i.e. an ideal voltage source in series with a 50 ohm resistance.  The measurements were made at 5.0 MHz, using a 100 MHz BW scope with a 10x probe (10 Megohm load).  With no load on the clk2 output, the output is a square wave swinging from rail to rail (~20 mV to +3.25V).  With a 50 ohm resistive load, coupled to the output by a 100nF capacitor, the output voltage swing is 725 mV p-p, or ~0 to 725mv at the clk2 pin.  If the clk2 output circuit were voltage driven, this implies a 1450 mV voltage source followed by a 50-ohm resistance.  It is anything but that.  With a 100 ohm resistive load, the p-p output voltage is 1375 mV, and with a 270 ohm load it is 2410 mV.  The current delivered to the 50 ohm load (725 mA/50 ohms) is 14.5 mA peak, and the currents to the 100 ohm and 270 ohm resistances are ~13.8 and 8.9 mA respectively.  So the output circuit appears to be a ~16 mA current source (8 mA average current for the square wave output; presumably the drive level for clk2 is set for 8 mA, but I do not have the source code for the sketch), at least for low resistance loads.  But the current oddly falls off as load resistance increases.  It appears as if there were an internal load resistance of a few hundred ohms in parallel with the external load.
I don’t know what all this analysis really amounts to, but I am sure the clock output only presents a 50 ohm resistive impedance to an external circuit when the output is itself terminated in 50 ohms.  Anyone care to elucidate?
14099 2017-06-28 20:15:07 Dana Myers Re: Si5351A: facts and myths
14100 2017-06-28 21:11:14 Dana Myers Roelof's measurement of Si570 vs Si5531A (was Re: [emrfd] Si5351A: f
14101 2017-06-28 21:14:50 Ashhar Farhan Re: Si5351A: facts and myths
The datasheet 0.95v revision repeatedly says that the output impedance is 80 ohms. I have used a series 33 ohms resistor feeding into a 6db pad. The other end of the pad drives a schottky diode mixer.

A slightly more elaborate scheme would be to use a darlington pair amplifier with a few milliamps current in the output transistor to keep the source impedance very low. This can be fed to the diode mixer with a series 47 ohms resistor.

- farhan

- f

14102 2017-06-28 22:15:56 Dana Myers Re: Si5351A: facts and myths
14105 2017-06-29 15:43:18 bwbangerter Re: Si5351A: facts and myths
14106 2017-06-29 17:22:32 Dana Myers Re: Si5351A: facts and myths
14107 2017-06-29 17:54:59 kb1gmx Re: Si5351A: facts and myths
Most of the logic types do not have a controlled impedance..

 Their output current is not proportional to the load resistance as at some point the output devices are pulled out of saturation (lowest impedance state) and into a constant current state (typical of fet type devices.).
In the constant voltage state the output impedance is typically low in the constant current state the impedance is increasing.

Its possible to draw a curve for output impedance but it is variable with supply voltage and total chip power drain.

for example most high level CMOS outputs are rated to 30ma thoug,h lower is normal, and the 5351 is 
not a high level output.  The total core current is limited to 45ma max so for three outputs the likely 
current is less than 10ma. The output impedance according to the datasheet is only valid if the high drive setting is invoked and the supply voltage is 3.3V and is a typical value.  its also specified at a specific frequency.  The problem is reconciling the problem of  3.3V in to 50 ohm you need 66ma  which by
spec cannot happen.  So that means if the source is 50 ohms to get 1.65V you still have to supply 33ma
again unlikely.  In the end the output drivers are not going to do as expected.  If the load is to great (too low resistance) the output devices will be force out of saturation and likely exhibit a higher than expected impedance.  Note if the load is reactive the waveform will distort as well.   Its a clock generator not 
RF source by design as its a clock generator for things like  Ethernet, USB, sound, HDMI, CPU base 
clock, serial interfaces,  and other timing needs so it plays by rules for saturating LVCMOS  circuits 
meaning its both current limited and maximum voltage limited.

For driving logic its mostly not a direct concern.  For driving cables and especially filters its a big deal.
Filters perform as stated when the terminations at both end are as specified.  The usual method is to 
isolate the filter from the device using attenuation (6db is common) or transformers. Both have liabilities.
The liability is lost signal power.  However gain is cheap at HF (2n3904 is cheap!) so an amplifier is 
needed to make up for the losses.

Its not a simple case but a complex one.  Trying to treat it like well understood deives like DBM or 
filters is not a reasonable task. But is useful none the less.

14108 2017-06-29 19:54:07 Dana Myers Re: Si5351A: facts and myths
14109 2017-06-29 20:05:25 rcbuckiii Re: Si5351A: facts and myths

So, can the Si5351 drive a level 7 diode mixer directly? Or does it need an amplifier followed by a 50 ohm attenuation circuit to insure proper drive level and impedance matching?

Ray, AB7HE
14110 2017-06-29 20:14:14 Hasan Murtaza Re: Si5351A: facts and myths
>I don’t know what all this analysis really amounts to, but I am sure the clock output only presents a 50 ohm resistive impedance to an external circuit when the output is itself terminated in 50 ohms. Anyone care to elucidate? 

If your scope has a 50-ohms input, you might try using that instead of the 10x probe. 
A 10x probe will not have an impedance of 10Mohms at 5MHz, but something more like 1.5 kohms (assuming 20pF input capacitance.) The capacitance of the probe (which is in parallel to it's resistance) dominates at HF frequencies, reducing it's input impedance. 

14111 2017-06-30 08:17:59 Roelof Bakker Re: Si5351A: facts and myths
Hello all,

I have measured the phase noise of the Si5351A as used in the QRP-LABS VFO kit and that of a Si570 used in a VFO kit from SDR-Kits.

I have used a PERSEUS SDR, running under Linrad with a filter bandwidth of 100 Hz. The S-meter of Linrad is a precise measurement tool, providing four decimal digits behind the dot. The values have been rounded to 0.1 dB as this is good enough.

As the intended use of the Si5351A is as a VFO for a 40 and 20 meter receiver with an IF of 9 MHz, the phase noise has been measured on 16 and 23 MHz at a spacing of 10, 20, 50 and 100 kHz.

Si5351A, at 16 MHz, spacing, phase noise in dBc/Hz:
10  - -124.0
20  - -126.2 
50  - -127.0
100 - -130.6

The noise around the carrier is not symmetrical. The above figures were found below the carrier. Above the carrier these were about 1 dB better.

Si5351A, at 23 MHz, spacing, phase noise in dBc/Hz:
10  - -123.3
20  - -124.9 
50  - -125.9
100 - -128.5

I am going to use the Si5351A as LO for a direct conversion receiver for NAVTEX on 490 and 518 kHz, so phase noise at 500 kHz was also measured:

Si5351A, at 500 kHz, spacing, phase noise in dBc/Hz:
10  - -125.5
20  - -128.1 
50  - -131.9
100 - -133.9

There were also a lot of spurs present at 100 dB below the carrier or more. I don't know what is the cause, but I gather that they won't be a problem.

Si570, at 16 MHz, spacing, phase noise in dBc/Hz:
10  - -138.2
20  - -135.1
30  - -132.6 
50  - -141.8
100 - -146.3

Si570, at 23 MHz, spacing, phase noise in dBc/Hz:
10  - -137.3
20  - -135.2
30  - -131.9 
50  - -141.4
100 - -145.5

Phase noise is peaking at a spacing of 30 kHz and this has been included in the table of the Si570.

Roelof, pa0rdt

14112 2017-06-30 08:45:21 winston376 Re: Si5351A: facts and myths

Excellent article/post.  Thank you for taking the time to give the community the benefit of your knowledge and experience.... Back-filled alot of holes in my knowledge of this ic family.

A question I have regards the 25/27 MHz fundamental reference crystal multiplication.  Your post states that the reference xtal is multiplied up to the 600-900 MHz VCO range. 

For the Si5xxx family, wondering how the multiplication of the reference xtal is done without adding drift error or multiplication error at 600-900 MHz?   

14113 2017-06-30 09:32:38 Bill Carver Re: Si5351A: facts and myths
Thank you for the very useful data Roelof.
14114 2017-06-30 09:44:29 swift_glen Re: Si5351A: facts and myths
I'd second Allison's note:
CMOS logic outputs are non-linear: trying to create a Thevenin model is an approach that'll get you into trouble.

Have tried characterizing HCMOS outputs, and found that output impedance varies considerably depending on the bias point. Mid-way between Vdd and Gnd, output Z rises considerably. Near ground, and near Vdd, output Z is lowest (similar to a MOSfet's Rds(on)). I'd bet that Si5351 output stages are similar, as Allison says.

What to do when a load wants significant current?
One option, as Allison suggests is to add a buffer amp to Si5351 output.
Here's an idea that I haven't tried, but might help to drive a low-Z load like a DBM mixer:
Program Si5351A to output the same frequency on two-of-three output pins. Invert one with respect to
the other (perhaps with 180 degree phase shift?). Now you have a differential output, taken between two CLKout pins. This helps in two ways - it eases the work of the VDDout bypass capacitor. It increases peak-to-peak output voltage. Now you can use a 4:1 step-down transformer to drive a low-Z load like a mixer. This will ease the current loading by half on the Si5351 output stages. Since drive will still be too high for a level 7 DBM mixer, a resistive attenuator (always a good idea) goes between Si5351 and mixer L.O. port.

One other caution: A really simple model of the Si5351 output stage looks like a small resistor (near 35 ohm?) alternately connecting between VDDout and Gnd. Half the time this small resistor conducts noise on the VDDout line to the CLKout pin. So VDD noise must be suppressed. Many DC supply regulator chips are notoriously noisy. If you're doing a direct-conversi
14115 2017-06-30 11:03:38 rcbuckiii Re: Si5351A: facts and myths

Thank you very much for those extensive measurements. They confirm that the Si5351A will be more than ample for my application. The Si570 has better phase noise numbers but for my receiver the Si5351A will work fine.

I have ordered a QRP-Labs Synth Kit and will begin level testing when I receive it.

14116 2017-06-30 11:16:16 bwbangerter Re: Si5351A: facts and myths
I appreciate all the information put forth regarding the use of the si5351a as an rf signal source.  It is now becoming clear to me that this is first and foremost a digital device, and the output circuit was never really characterized as an rf source.  It looks to me that the best route to using this chip as we EMFRDers are prone to do in the hf and low vhf range is to buffer the output, with an amplifier with a fairly high input impedance that does not load the chip's output excessively, and a well-characterized 50 ohm output impedance.  I am a fan of emitter followers for providing a 50 ohm resistive impedance over a wide frequency range.
14117 2017-06-30 21:26:40 AD7ZU Re: Si5351A: facts and myths
Thanks Hans for a superb explanation into the details of the Si5351 amid the always marginal SL documentation!

I am planning on using Si5351C for the current project and 6 of the 8 outputs. (rx, tx, codec, and an alignment signal)
also using an external TCXO for improved temp stability.
The clock in spec goes to 100mhz vs the 25mhz external xtal This may improve the phase noise / jitter?  



14120 2017-07-01 12:45:40 Dana Myers Re: Si5351A: facts and myths
14121 2017-07-01 12:52:46 Dana Myers Re: Si5351A: facts and myths
14122 2017-07-01 13:50:06 kb1gmx Re: Si5351A: facts and myths
It should but considerable care to route the signal is needed to keep the square edged from ringing like a struck bell.     Those edges if they ring will introduce a lot of unacceptable stuff into the mixer.

to drive a DBM you only need a 5-7 dBm or about a volt Pk-PK.

14123 2017-07-01 14:01:02 Bill Carver Re: Si5351A: facts and myths
Doesn't the data sheet say that you can use a 100 MHz reference, but if you do it's divided by four at the input? In which case there is no improvement at all.

14124 2017-07-01 14:12:49 Dana Myers Re: Si5351A: facts and myths
14125 2017-07-01 14:20:15 jgaffke Re: Si5351A: facts and myths
In the Bitx20 group we're running into limits on flash available, so I wrote  some functions to reduce the footprint for Si5351 support.  About 30 lines of working code, parked at   https://groups.io/g/BITX20/files/KE7ER/si5351bx_0_0.ino
A few things I've learned about the part:

It's one of a family of parts, looking over the Si5338 datasheet is instructive as that document is a bit more complete.  Page 13 shows that iitter with a fractional output divide is not all that much worse than integer mode. Page 20 states that output divider fractional mode works for ratios of 8.0 on up,  we must use integer values of 4 or 6 to achieve the higher output frequencies.  (This is consistent with how the Si5351 seems to work, but not consistent with SiLabs AN619.)  Also on page 20, it describes how the multisynth dividers achieve such low jitter by digitally predicting the amount of phase shift needed at each clock edge to best approximate the required output clock.

It takes 8 register writes to update a multisynth divider, I was expecting a lot of jumping around in the output frequency as each register write took effect.  That was not the case.  Updating the output multisynth divider for clocks at 1 Hz increments produced a pure tone in a shortwave receiver that sounded like an analog VFO slewing, and no hint of runt cycles showed up on the scope.

There are a bunch of libraries out there for handling the Si5351.  The commonly used Etherkit library uses fractional output divides by default with a fixed VCO frequency (this can be overridden) unless the requested frequency is over 100mhz, as this allows the independent use of all three Si5351 outputs.  Hans' library uses integer mode on the output divider, varying the VCO to hit the required frequency, this gives lower phase noise but restricts us to two independent clocks as we only have two VCO's.  The later devices in the family such as the Si5338 and Si5341 only have one VCO, you must use fractional output divides to get multiple independent frequencies.

The Bitx has been using the Etherkit library thus far with good results, and we could make use of all three clocks.  A fixed VCO makes for simpler code, as the output multisynth divider has a much wider range than the VCO feedback multisynth.  So the code I wrote follows Etherkit's lead on that.

Jerry, KE7ER

14126 2017-07-02 00:27:15 Dana Myers Re: Si5351A: facts and myths
14127 2017-07-02 12:17:39 AD7ZU Re: Si5351A: facts and myths
Bill is correct
per my latest datasheet (rev 1.0)  the clkin is divided to 30mhz max ahead of the PLLs in the B and C parts.
the root reason for the external TCXO was improved temp stability. I am looking at a 54mhz TCXO to /2 to 27
There may or may not be an improvement in the final output specs?
the B and C parts also use 4 independent VDDO output buffer power pins to separate output buffer power rails.  from the datasheet it appears this feature is there to allow the 5351 to drive a variety of logic families.  I don't know how much isolation is required?  a single regulated VDDO line with separate bypass caps at each VDDO pin may be sufficient?

i have been working
14130 2017-07-02 14:24:43 Dana Myers Re: Si5351A: facts and myths
14131 2017-07-02 18:31:11 AD7ZU Re: Si5351A: facts and myths
Thanks all,

I am archiving this entire thread and soon will get started on the VFO/codec clock.  There is more info
14132 2017-07-02 19:29:09 jgaffke Re: Si5351A: facts and myths
The cheap MSOP10  is speced for a rererence between 25 and 27mhz, the others with a dedicated reference clock pin (separate from the crystal oscillator) are 10 to 40mhz with a divider if your reference exceeds 40mhz.  Hans says in post 13827  that driving the crystal osc pin outside spec will cause performance to suffer:   "You *can*, some QRP Labs kits constructors tried this, and it does work. But the output spectral purity suffers a lot, in some cases. It appears that the internal PLL in the Si5351A is optimised for the range 25-27MHz. "

Jerry, KE7ER

---In emrfd@yahoogroups.com, wrote :
i did note in the data sheet that the A and B parts could use an external reference also, its just piped into the Xa pin with the Xb pin floating.
14136 2017-07-03 21:02:42 jgaffke Re: Si5351A: facts and myths

If only using PLLA on the Si5351, what should be done with PLLB?
I see nothing in AN619 about shutting down either PLL, 
and the feedback msynth registers are not initialized at power up.