11900	2015-11-21 06:41:56	Ashhar Farhan	a new low phase noise clock from si
Message	Date	From	Subject
comrades, here is some fresh meat: http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5380.pdf it is on page 35. -136 dbc at 10 khz. - f
11901	2015-11-21 06:42:23	Ashhar Farhan	Re: a new low phase noise clock from si
page 30, actually.
11902	2015-11-21 10:10:17	Bill Meara	Re: a new low phase noise clock from si
Wow, 12 outputs. I am right in thinking that we could set this up with a fixed BFO/carrier freq and then a tunable VFO freq? Or 11 other tunable VFO freq ranges?
11903	2015-11-21 10:17:57	Ashhar Farhan	Re: a new low phase noise clock from si
well, there might be cross talk. given that all those are on the same silicon. i gather that the chip itself is cheap. it might make sense to use one per required signal. there is no point in running a multi-operator, multi-band contest with a single chip. - f
11904	2015-11-21 11:34:17	vasilyivanenko	Re: a new low phase noise clock from si
Thanks F Read about it last June in this very interesting 'review' of the product -- comparing the Si DSPLL architecture to previous low jitter, conventional cascaded PLL + external VXCO assemblies. http://www.edn.com/design/analog/4439729/1/Optimizing-clock-synthesis-in-small-cells-and-heterogeneous-networks [4 pages] My understanding is that "the high-performance ultra-low-phase-noise analog 14.7456 GHz VCO" = an analog low phase noise L - C VCO, that of course, gets divided down. Si5380 Reference Manual online http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5380-RM.pdf "The DSPLL provides the synthesis for generating the output clock frequencies which are synchronous to the selected input clock frequency or free run from the XTAL. It consists of a phase detector, a programmable digital loop filter, a high-performance ultra-low-phase-noise analog 14.7456 GHz VCO, and a user configurable feedback divider. An internal oscillator (OSC) provides the DSPLL with a stable low-noise clock source for frequency synthesis and for maintaining frequency accuracy in the Freerun or Holdover modes. The oscillator simply requires an external, low cost 54 MHz fundamental mode crystal to operate. No other external components are re-quired for oscillation. A key feature of DSPLL is providing immunity to external noise coupling from power supplies and other uncontrol-led noise sources that normally exist on printed circuit boards." Best! T
11905	2015-11-21 12:49:37	Lasse Moell	Re: a new low phase noise clock from si
Not only that but it may be problematic to have specific frequencies at the output, based on one PLL and then dividing the output. Still looks pretty interesting and hopefully will be cheap enough for hams to explore!! /Lasse SM5GLC 21 november 2015 19:17:55 +01:00, skrev Ashhar Farhan farhanbox@gmail.com [emrfd] : well, there might be cross talk. given that all those are on the same silicon. i gather that the chip itself is cheap. it might make sense to use one per required signal. there is no point in running a multi-operator, multi-band contest with a single chip. - f
11906	2015-11-22 07:09:10	jorschei	Re: a new low phase noise clock from si
Hi Lasse, We PA0RWE and I have design the Si5351A in the sampler ( mixer ) from Dan Tayloe and thad work well. The noise is divided bij 4, work up to 30 MHz. See RWE site where the I&Q base band signals are procesed in the PSoC5. Listen to the sound files they are good. no jitter problem.... Good RF PCB design is important.... I wander if the the 12 output's of the 80 version will not produce noise in a receiver design ? And 13 dollar +... 73'Joris PE1KTH PSoC SDR
11907	2015-11-22 14:14:31	Steve Dick	Re: a new low phase noise clock from si
Hi Ashhar. I haven’t looked at this part in detail, but do you have a feel for how this part compares to the SI570? The SI570 data sheet specs in terms of phase jitter; the SI5380 in terms of dbc/hz plots. I was thinking if one could provide an accurate ref clock at the required 54 MHz, one could make a dynamite relatively low cost and accurate clock generator. I need two low phase noise clocks one fariable, one fixed for a general coverage receiver I am working on. I came across a low cost TCXO chip on the Hermes Lite yahoo group that Steve KF7O mentioned. It is the Fox 924B series. It has a 2.5ppm temperature stability. One could get the 27MHz version and make a frequency doubler circuit to 54 MHz needed by the SI5380. Phase noise for the Fox 924B is not specified. And I know, I know, you’re adding 3 dB of additional phase noise at 54 MHz doubled output. Don’t know if its net phase noise would degrade the phase noise of the SI5380. The SI5380 only costs $14.70 or so, and the Fox 924B-27.000 only costs $2.73 or so. So with a little frequency doubling circuit on the ‘924B seems to me one could make a helluva nice, stable, multi-output reference generator. What do you think? “Digital Steve”. K1RF
11908	2015-11-24 04:09:40	victorkoren	Re: a new low phase noise clock from si
Reading the datasheet it seems to me that this is an integer number PLL which means that you cannot generate any wanted frequency as with a fractional N PLL, only specific frequencies in the nature of (Fref /R) *N when N and R are integers. Victor - 4Z4ME