EMRFD Message Archive 1087

Message Date From Subject
1087 2007-10-15 01:04:26 neomag_magneo AGC-range in mosfet if-amplifier chain
Dear group,

I am finalizing (if this is possible for any homebrew equipment !) my
receiver based on a H_mode mixer, DDS-vfo ansd a three-stage mosfet
if-amplifier chain (8 MHz if). When operating and testing the rx, I
have been concerned by the quite limited agc-range. One obvious
reasons seems to be the tendency to oscillate at higher gains, which
means that the g2-voltage (AGC) is limited to max. 2.5 V with the
source at 2 V (red led as the bias element). With increasing input
level this goes down to 1.5 V (1 volt change), which however, seems to
do the job and save my ears. The AGC generator is the one in EMRFD
with hang option included.

All three if-stages have tuned circuits at the drains, which might
explain the oscillation tendency. Quite rarely I have seen such
arrangement, most if-amps are broadband these days. Would it be
feasible to reduce the gain by modifying the drain circuitry, since
the narrowband if amp operation is not really an issue (I have 4 poles
of crystal filtering after the amp to cut down the noise generated).
This would allow higher voltage at g2 and larger swing (I think !).


Heikki Ahola (OH2LZI)

P.S. Is the AGC-curve for various mosfets roughly the same as in 40673
or are there big variants. I am not 100 percent sure of my mosfets,
but BF981 is a good guess...
1088 2007-10-15 06:26:50 Allison Parent Re: AGC-range in mosfet if-amplifier chain
1091 2007-10-15 10:55:55 Wes Hayward Re: AGC-range in mosfet if-amplifier chain
Hi Heikki, Allison, and group,

Good questions Heikki, along with great answers from Allison. It's
been a very long time since I have built a dual gate mosfet RF/IF
amplifier with both gate and drain tuning. There is just too much
available gain to pull this off with ease. As Allison said, you
can tack a resistor load across the drain coil to force the gain
down. Note the design in EMRFD Fig 6.56: There is a 2.2K
resistor in the gate of the second and third stages. The capacitor
coupling from the previous drains means that this R is the drain
load. That low R value keeps the gain down and aids stability.

There can be quite a variation in available gain with the dual gate
parts. The BF998 SMT part that I talk about on my web site (now at
http://w7zoi.net/ ) is really hot compared with some of the older
leaded parts. (Yep, the free parts are still available from Bob

I presented a paper at FDIM in Dayton (coauthored with buddy Jeff,
wa7mlh) last spring on a "new" variation on this theme. That paper
is in the proceedings for that conference, which was sponsored by QRP-
ARCI. Essentially, the dual gate mosfet or a cascode with two FETs
is replaced by what we called a "hybrid cascode." This consists of
a cascode amplifier with a JFET on the bottom and a bipolar on top.
We used J310s and 2N3904s, but this is not especially critical.
(Hey, we all have our "favorites.") There is prior art kicking around
for this topology, so it is not really new. But it is nonetheless a
very useful circuit.

The design in EMRFD Fig 6.50 has performance problems when the power
supply drops. But when we do a new variation with 2N3904s on top,
Vcc can drop to 6 volts while remaining operational. The final
circuit that Jeff and I built uses three stages and an AGC
detector/amplifier much like that in the IF strip for the old
Progressive Receiver from QST, Nov 81.

One of the virtues of the hybrid cascode circuit is that it is easily
simulated in SPICE so long as you have some reasonable JFETs. The
J310 has much tighter Idss and Vp windows than parts like the the MPF-
102. There are some other JFETs out there (I forget the part
number, for they never made it to my "favorite" list) that are even
better in this regard. I saw one spec sheet (I think it was
Phillips) that only had a 1.5:1 Idss range, which is wonderful.

When I built my version of the new circuit, I used the "Ditter" from
EMRFD Fig 7.77 and that was really useful. I have modified the
Ditter, eliminating the 555 timer. Instead, I now use a Wavetek
Model 145 pulse generator as the control. I did most of my testing
with pulses that were 0.1 to 1 mS wide, with a rep rate of 1 per
second. Generally, we spent a lot more time with the latest version
of this circuit than we did with the original 1981 QST circuit or the
variations that are in EMRFD. I built an "ugly" version with
leaded parts, and then a PCB version with SMT parts. Jeff has also
built several and has them operating in some of his SSB
transceivers. K5IRK has built one and has it operating in a version
of the 81 QST receiver.

Incidentally, that 1981 QST IF circuit has been duplicated by some
folks with the BF998 SMT parts without difficulty. Indeed, it can
be easier to build in SMT, for it becomes easy to get a really good
bypass on the gate-2 leads, which then kills the UHF instability

The details on our hybrid cascode amplifier will be in print before
too long, so I'm not going to post any circuits here.

73, Wes
1093 2007-10-16 04:46:32 neomag_magneo Re: AGC-range in mosfet if-amplifier chain
Dear all,

Mni tnx for Allison and Wes for the advice and comments. This is not
the first time I have encountered the instability problem in my if
amplifiers but previously shunting the tuned circuit in the MOSFET
drain has more or less fixed the problem. With this background I did
include the resistors in my design, therefore it is obvious that some
other measures are needed to tame the circuit (shielding, bypassing
etc.). On the other hand, like I said, the operation of the rx is
quite satisfactory right now and some other sections (e.g. drifting
BFO) might need fixing more urgently.

As I see it, the if amp instability limits the usable gate2 voltage
at 2.5 V ( about 0.5 V above the source biased with a red LED).
Something like 4 - 5 V would increase the gain up to the maximum. If I
can get rid of the instability, even at cost of the overall gain,
would I still benefit from the improved AGC range by gate2 voltage ?
This seems to be the case, since my if amplifier is sitting in the
middle of the AGC curve at no signal.


Heikki (OH2LZI)
1094 2007-10-16 05:45:57 Allison Parent Re: AGC-range in mosfet if-amplifier chain
1096 2007-10-16 05:57:12 Allison Parent Re: AGC-range in mosfet if-amplifier chain
1100 2007-10-17 00:19:06 neomag_magneo Re: AGC-range in mosfet if-amplifier chain/ BFO drift
Dear group,

Thanks again !

After some thinking I have to admit of being aware of all the
precautions which would prevent if oscillations, shielding, ferrite
beads etc. Need to improve those in my design as time and contest
operation allows. Right now the rx involved is the only one I possess,
the other one based on the famous "Progressive Receiver" previous one
was left at my summer qth which is quite inaccessible during the
winter, hihi.

The bfo drift I mentioned was not a problem in any rx until I started
up with psk31. What I have right now is a free running 468 kHz LC-osc
(the rx is actually a double super) which needs slight adjustment
every once in a while (when warmed up properly !). The tradional way
could be temperature compensation with N750/N330 capacitors, another
way that occurred to me is a 5-10 MHz LC-osc with a stabilizer
(huff-and-puff) and division down to second if frequency. At least in
theory this should provide sub-hertz stability required. Another
option, DDS for bfo sounds a little bit like overkill. BFO crystal osc
is a straightforward solution but only if one already has all the
crystals needed (which I do not !).

73 de Heikki (OH2LZI)